Design of a CMOS Parallel Counter with Improved Operating Frequency

Abstract

Counters are one among the basic building block in
every digital system. It is an essential building block for a variety of circuit operations such as programmable frequency dividers, shifters, code generators and various arithmetic operations. Since these fundamental operations comprises of many applications main focus is for an efficient counter design. In this paper a new parallel counter is designed that achieve high operating frequency. The high operating
frequency is achieved by pipeline partitioning methodology which consists of a counting path and a state look ahead. The counting path’s counting logic controls counting operations and it consist of 2- bit counting modules. State look ahead path’s state look ahead logic anticipates the future states and thus prepares the counting path for these future states. In this counter architecture there are three simple
repeated CMOS logic modules types: an initial module generates anticipated counting states for higher significant bit modules through state look-ahead path, simple D-type flip-flops and 2-bit counters. The state look-ahead path prepares the counting paths next counter state with respect to clock. The clock edge triggers all modules
simultaneously thus concurrently updating the current state with a uniform delay with all counting modules. Here, as an example a 8-bit counter is designed with the pipeline partitioning methodology and is simulated by DSCH & Microwind tool. The structure is scalable to
arbitrary N-bit counters using the three module types.