Open Access Open Access  Restricted Access Subscription or Fee Access

Understanding Different ADC Parameters used in Software Radio for 3G/4G Mobile Receiver

Preeti Trivedi, Dr. Ajay Verma

Abstract


A software defined radio adopts a fully reconfigurable      front end and is believed to be the right answer to realize 3G/4G mobile systems. This paper will give a review of different   ADC architecture used in SDR mobile receiver with different parameter of ADC. In an ideal software radio, the data conversion    process   occurs   immediately   after the antenna in the receiver chain. This paper also presents a multi-standard reconfigurable   modulator, which are able to support the predictable standards of fourth generation of mobile communication systems (4G). The down conversion process is entirely in the digital domain. The proper selection of data converters, both analog to digital converters and digital to analog converters (DACs) is one of the most challenging steps in designing software radio. Different types of ADCs are discussed here.

Keywords


Analog to Digital Converter (ADC), Intermediate Frequency (IF),Software Defined Radio (SDR), SNR, Radio Frequency (RF).

Full Text:

PDF

References


Software radio – A modern approach to Radio Engineering – Jeffery H Read, Pearson education-2002

Design of Rf/IF analog to Digital converters for software Radio Communication Receivers – Bharath kumar Jhandri – Phd thesis, May 2006.

B. Boser and B.wooley, “The design of Sigma Delta modulation analog is digital converters” IEEE J. Solidstate circuits, vol.33 . PP 1298-1308 Dec 1990.

R Wilden, “Analog to Digital converters survey and analysis,”” IEEE J select areas communicate, vol. 17 pp539-550 Apr 1999 ”.

T.Hentschel,M.henker and G.Fettweis,”The digital front end of software radio terminals”,IEEE Personal communications,vol. 6,pp 40-46,Aug 1999

J.Mitola, III,”The software radio architecture,IEEE Communications magazine, vol.38, pp 138-143, Sep 2000

R. H. Walden, “Analog-to-Digital Converter Survey and Analysis,” IEEE J. Select. Areas Commun.,vol. 17, no. 4, pp. 539–550, Apr. 1999

H. Kobayashi, M. Morimura, K. Kobayashi, and Y. Onaya, “Aperture Jitter Effects in Wideband ADC Systems,” in Proc. 6th IEEE International Conference on Electronics, Circuits and Systems(ICECS 99), Pafos, Cyprus, Sept. 1999, pp. 1705– 1708.

Hai Tao,Laszlo Toth and John M n Khoury,”analysis of Timing Jitter in Bandpass Sigma-Delta Modulators”in IEEE trans. On circuits and systems-II: Analog and digital signal processing,vol.46,no. 8,Aug. 1999.

Georges Gielen,”A desigh Approach for Power –Optimized Fully Reconfigurable ∑∆ A/D Converter for 4G Radios,” in IEEE transactions, Circuit and system-II,vol.55,NO.3, pp.229-233.

M. Gerhard, C. Ebner, S. Mechnig, T. Blon, C, Holuigue, and E. Romani, “A 20-mW 640-MHz CMOS continuous-time ∆∑ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2461–2469, Dec. 2006

Paul T.M. Van Zeijl, Robeet H.M. Van Veldhoven, Peter A.C.M.Nuijlen “Sigma – Delta ADC Clock jitterin digitally implemented Receiver Architectures”in proceedings of the European Conference on wireless Technology,Sept. 2006, Manchester, UK.

Y. Fujimoto, Y. Kanazawa, , P. Lore, and M. Miyamoto,“An 80/100MHz/s 76.3/70.1-dB SNDR_∆∑ADC for digital TV receivers,” in Dig.Tech Papers ISSCC, Feb. 2006, pp. 201–210.

T. Christen, T. Burger and H. Quiting, “A 0.13 um CMOS EDGE/UMTS/WLAN tri-mode_∆∑ADC with - 92 THD,” in Dig. Tech Papers ISSCC, Feb. 2007, pp. 240–241.

S. Ouzounov, R. van Veldhoven, C. Bastiaansen, K. Vongehr, R. van Wegberg, G. Geelen, L.Breems, and A. van Roermund, “A 1.2v 121-mode CT _∆∑ modulator for wireless receivers in 90-nm CMOS,” in Dig. Tech Papers ISSCC, Feb. 2007, pp. 238–239.

R.SCHreier,”An empirical study of high-order single bit delta sigma modulator”IEEE Trans.CircuitsystemII analog digital signal processing vol.40.no.8, pp461-466,Aug 1993.

Jan Craninckx, Georage Gielen “A Design Approach for Power–Oprimized Fully Reconfigurable ∆∑ADC converter for 4G Radios”in IEEE Transaction on Circuit and System-II , ,vol.55, no.3, March 2008.

Scott D.Kulchycki, Roxana Trofin,Katelijn Vleugels Bruce A.Wooley,”A77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/ Discrete-Time Cascaded ∑∆ Modulator”, IEEE journal of Solid-State Circuits, vol.43, No. 4 April 2008.

Hairong chang.hua tang “A simple technique to reduse clock jitter effects in continous –time delta sigma modulator” IEEE 2008.

Mathew z.strayer and Michacl H.perritt,”A 12 bit,10 MHz Bandwidth ,continuous time sigma delta ADC with 5 bit, 950MS/s VCO based quantizer.”IEEE Journal of solid state circuits,vol 43, no.4, April 2008,pp805-813.

V.Christo Flakis, A.A Alexendridis,P. Kostarakis and K.Dangars “Analog to Digital converter ‘a key concept in the implementation of a 3G software Defined Radio Receiver” International Journal 2002.

Mark S. Oude Alink, André B. J. Kokkeler, Eric A. M. Klumperink, Kenneth C. Rovers, Gerard J. M. Smit, and Bram Nauta, “ Spurious-Free Dynamic Range of a Uniform Quantizer”, IEEE Transactions on Circuits and Systems-II,Vol.56,June 2009.pp 434-438.

Mark S. Oude Alink, André B. J. Kokkeler, Eric A. M. Klumperink,’’Spurious-Free Dynamic Rangeof a Uniform Quantizer” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 6, JUNE 2009.

Christopher R. Anderson and Jeffrey H. Reed, “Performance Analysis of a Time-Interleaved sampling Architecture for a Software Defined Ultra Wideband Receiver”, Proceeding of the SDR 05 Technical Conference and Product Exposition. Copyright © 2005 SDR Forum. All Rights Reserved


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.