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Computer Aided Partitioning for Design of Parallel Testable VLSI System

M.R. Ezilarasan, D. Uthirapathi


Design automation is a challenge for tool designers, due to increasing complexity of building VLSI circuits with molecular and nano-scale precision. Recent emerging complex problems in the field of VLSI design can be easily solved through the divide and conquer approach using partitioning methods. Although, partitioning problem has major importance in the field of VLSI design automation, it is treated with a testing perspective in this paper. This facilitates to address the reliability and testability issues of VLSI systems during the early product development stages. An automated VLSI design tool for partitioning combinational CMOS circuits that can create parallel testable VLSI circuits is developed and discussed. This computer aided tool can optimize the design constraints of test time and hardware overhead for design-for-testability (DFT) by an exploration of the solution search space. After partitioning and optimization, a considerable reduction in the length of test vectors is obtained.


Directed Acyclic Graph, Circuit Under Test, Linear Feedback Shift Register, Built in Logic Block Observer, Multiple Input Signature Analyzer

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Sabih, H.G.: Algorithms for VLSI Design Automation. Wiley, Netherlands (2009)

K. S. Kumar, U. P. Bhaskar, S. Chattopadhyay, and P. Mandal, “Circuit Partitioning using Particle Swarm Optimization for Pseudo-Exhaustive Testing,” In: International Conference on Advances in Recent Technologies in Communication and Computing, pp. 346—350, October 2009.

I. Voyiatzis, D. Gizopoulos, and A. Paschalis, “Recursive Pseudo-Exhaustive Two-Pattern Generation,” IEEE Transactions on VLSI Systems, vol. 18, pp. 142—152, January 2010.

W. B. Jone, and P.A.Christos, “A Coordinated Circuit Partitioning and Test Generation Method for Pseudo-Exhaustive Testing of VLSI Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, pp. 374-384, March 1995.

D. E. V. Bout, and T. K. Miller, “Graph Partitioning using Annealed Neural Networks,” IEEE Transactions on Neural Networks, vol. 1, pp. 192—203, June 1990.

R. Srinivasan, S.K.Gupta, and M.K. Breuer, “Novel Test Pattern Generators for Pseudo-Exhaustive Testing,” IEEE Transactions on Computers, vol. 49, pp. 1228 – 1240, November 2000.

B. Shaer, D.Landis, and S. Al-Arian, “Partitioning Algorithm to Enhance Pseudo-exhaustive Testing of Digital VLSI Circuits,” IEEE Transactions on VLSI systems, vol. 8, pp. 750 –754, December 2000.

S. Hellebrand, and H.J. Wunderlich, “Tools and Devices supporting the Pseudo-Exhaustive Test,” In: Proc First European Design Automation Conf., pp.13—17, March 1990.

R. Srinivasan, S.K. Gupta, and M. Breuer, “An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing,” In: Proc. Design Automation Conf., pp. 242—248, June 1993.



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