Open Access Open Access  Restricted Access Subscription or Fee Access

Reduction of Switching Losses and Current Ringing Effects in SiC JFET-Si MOSFET Cascode Switch using an Enhanced Gate Driver

J. Kingsley Femina, J. Mangaiyarkarasi


SiC based power switches are used to improve the performance of PV converters at high operating frequency, voltage and temperature. In this paper SiC JFET-Si MOSFET cascode configuration is used as a power switch. To fully utilize the excellent characteristics of SiC JFET, a low voltage Si MOSFET and a high voltage SiC JFET cascode configuration is used. Enhanced two stage dc coupled gate driver circuit is proposed to drive the SiC-Si cascode switch. It reduces switching losses and system volume. In addition to that parasitic dampening methods are used to reduce current ringing effects. SiC-Si cascode configuration with proposed gate driver circuit provides high efficiency and high power density.


Current Ringing Effect, Enhanced Gate Driver, Parasitic Dampening, SiC JFET, Si MOSFET.

Full Text:



Daniel Aggeler, Francisco Canales, Juergen Biela and Johann W. Kolar, ―dv/dt-Control Methods for the SiC JFET/Si MOSFET Cascode,‖ IEEE Trans. Power Electron., vol. 28, no. 8, August 2013.

G. Massobrio and P. Antognetti, ―Semiconductor Device Modelling with SPICE,‖ 2nd ed., McGraw-Hill, 1998

P. Friedrichs, H. Mitlehner, K-O Dohnke, D. Peters, R. Schorner, etc. ―SiC power devices with low on-resistance for fast switching applications,‖ ISPD, pp. 213-216,2000.

P. Friedrichs, H. Mitlehner, K-O Dohnke, R. Schorner and R. Elpelt, ―The vertical silicon carbide JFET – a fast and low loss solid state power switching device,‖ proc. EPE 2001, 2001, CD-ROM.

P.Friedrichs, ―Silicon carbide power devices—Status and upcoming challenges,‖ in Proc. Eur. Conf. Power Electron. Appl., Sep. 2007, pp. 1–11.

R. Kelley and M. S. Mazzola, ―SiC JFET gate driver design for use in DC/DC converters,‖ IEEE Trans. Power Electron., 2006.

A. Orellana and B. Piepenbreier, ―Fast gate drive for SiC-JFET using a conventional driver for MOSFETs and additional protections,‖ in Proc. 30th Annu. Conf. IEEE Ind. Electron. Soc., Nov. 2004, vol. 1, pp. 938-943.

J. Biela, U. Badstuebner, and J. W. Kolar, ―Design of a 5-kW, 1-U, 10-kW/dm3 reasonant DC-DC converter for telecom applications,‖ IEEE Trans. Power Electron., vol. 24, no. 7, pp. 1701-1710. Jul. 2009.

I. Josifovic, J. Popovic-Gerber and J. Ferreira, ―Improving SiC JFET switching behavior under influence of circuit parasitic,‖ IEEE Trans. Power Electron., vol. 27, no. 8, pp. 3843-3854, Aug. 2012.

L. Yang and W. G. H. Odendaal, ―Measurement based method to characterize parasitic parameters of the integrated power electronics modules,‖ IEEE Trans. Power Electron., vol. 22, no. 1, pp. 54-62, Jan. 2007.

Y. Wang, C. J. Cass, T. P. Chow, F. Wang and D. Boroyevich, ―SPICE model of SiC JFETs for circuit simulations,‖ in Proc. IEEE Workshop Comput. Power Electron., Jul. 2006, pp. 212-215.


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.