Open Access Open Access  Restricted Access Subscription or Fee Access

Design and Implementation of Novel ‘n’-bit Inverter and Buffer using Reversible Gates in QCA

P. Vanjipriya, R. Gowri Shankar


Moore’s law states that the number of transistors that could be integrated into a single die would grow exponentially with time. Thus this causes increasing computational complexity of the chip and physical limitations of devices such as power consumption, interconnect will become very difficult. According to recent analysis the minimum limit for transistor size may be reached. Thus, it may not be possible to continue the rule of Moore’s law and doubling the clock rate for every three years. So in order to overcome this physical limit of CMOS-VLSI design an alternative approach is Quantum dot Cellular Automata (QCA).in inverter and buffers a majority gates plays a vital role. In this survey a   novel programmable inverter/buffer using XOR-Logic is taken for analysis and a new programmable novel inverter/buffer is designed based upon QCA technology. This modified novel reversible gates used in the design. This will lead to reduce number of QCA cells so that total area and circuit complexity of inverter/buffer can be minimized compare to previous designs. It also achieves reduced power consumption and high speed performances than all other existing and conventional X-OR gates design which uses normal inverter/buffer.


Moore’s Law, CMOS, Area, Power Consumption, Quantum Dot Cellular Automata (QCA), Reversible Gates, Inverter/ Buffer.

Full Text:



C. S. Lent, P. D. Tougaw, W. Porod, and G. H. Bernestein, “Quantum cellular automata,” Nanotechnology, vol. 4, no. 1, pp. 49–57, 1993.

The National Technology Roadmap for Semiconductors. Semiconductor Industry Association, 1997.

M. T. Niemer and P. M. Kogge, “Problems in designing with QCAs: Layout = Timing,” Int. J. Circuit Theory Appl., vol. 29, no. 1, pp. 49–62, 2001.

K. Walus, G. A. Jullien, and V. S. Dimitrov, “Computer arithmetic structures for quantum cellular automata,” in Proc. Asilomar Conf. Sygnals, Syst. Comput., Nov. 2003, pp. 1435– 1439.

Stefania Perri, Pasquale Corsonello, and Giuseppe Cocorullo” Area Delay Efficient Binary Adders in QCA”IEEE transactions on very large scale integration (vlsi) systems, vol. 22, no. 5, may 2014.

]Rajitha Chandragiri, 2, P. Venkata Lavanya International Journal of Computational Engineering ResearchVol,03Issue, 8 Design and Testing Of Prefix Adder for High Speed Application by Using Verilog HDL.

P.D. Tougaw and C.S. Lent. Logical devices implemented using quantum cellular automata. Journal of Applied Physics, 75:1818, 1994.

Namit Gupta, K.K. Choudhary and SumantKatiyal “One Bit Arithmetic Logic Unit (ALU) in QCA” Int. J. on Recent Trends in Engineering and Technology, Vol. 8, No. 2, Jan 2013

Rajeev Kumar et al. Int. J Engineering Science and Technology “Design & Implementation of Majority Gates on FPGA & Comparison of Area Power Tradeoff”,ISSN : 0975-5462 Vol. 4 No.04 April 2012” pg no:1734-1740

H. Cho and E. E. Swartzlander, “Adder design and analyses for quantum-dot cellular automata,” IEEE Trans. Nanotechnol., vol. 6, no. 3,pp. 374–383, May 2007.

H. Cho and E. E. Swartzlander, “Adder and multiplier design in quantum-dot cellular automata,” IEEE Trans. Comput., vol. 58, no. 6, pp. 721–727, Jun. 2009.

V. Pudi and K. Sridharan, “Low complexity design of ripple carry and Brent–Kung adders in QCA,” IEEE Trans. Nanotechnol., vol. 11, no. 1, pp. 105–119, Jan. 2012.

S. Perri and P. Corsonello, “New methodology for the design of efficient binary addition in QCA,” IEEE Trans. Nanotechnol., vol. 11, no. 6, pp. 1192–1200, Nov. 2012.


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.