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Low Power Hybrid Arithmetic Units with Adaptive Clocking for FFT Applications

K. Saranya

Abstract


Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic units designed. Various adder families have been proposed in the past to tradeoff speed, power and area for possible use in ALUs. It includes careful optimization of existing and improved arithmetic units by mixing fast arithmetic units in to slower ones i.e, latency predictor block is used. The improved Ling adder has 40% less power consumption, delay and area than the conventional adders so it is used in the further design of FFT. The throughput, hardware costs, area and power increases due to multiple data path along the stages in FFT approach. By comparing the area, power and delay of the improved adders with conventional, Ling adder is used in Radix-4 FFT approach. The delay of Radix-4 FFT approach with Ling adder gets reduced. The adaptive clocking is applied to the FFT design where the critical path of design is reduced. Power consumption of adders is analyzed using Synopsys design compiler, T-spice S-Edit and delay using Xilinx. The layout of Ling adder is obtained with 180nm technology.

Keywords


Arithmetic Logic Unit, High-Speed Design, Low Power Adders, Latency, Fast Fourier Transform

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References


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