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High Speed Area Efficient VLSI Structure for Real Time Image Computing

V. P. Abithamol, E.P. Sumesh, R. Vidhyalavanya


A VLSI architecture capable of real-time 2-D Discrete Wavelet Transform computing is proposed in this paper. The proposed architecture-- based on a new and fast convolution approach-- reduces the hardware complexity and a reduction in the critical path of the multiplier block. The architecture with an efficient utilization of memory area, produces one output in every clock cycle. As a result, real time DWT computation is feasible. The system is verified - using JPEG2000, on Xilinx Virtex-II Field Programmable Gate Array (FPGA) device without accessing any external memory.For an image size of 256x256 pixel a computation rate more than 270Msamples/s and a memory requirement of lessthan 16kb is the outcome of the proposed model. The proposed design requests reduced memory and provide very high-speed processing as well as high PSNR quality.


Discrete Wavelet Transform (DWT); Fast Convolution; FPGA; VLSI.

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