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Closed Form Expression for Low Voltage Using Power Gating CCMOS (Clocked CMOS) D-Flip Flop

N. Bharathi, P. Divya, M. Jayasurya, A. Udhayakumar


In Advanced computing system High speed, power is important parameter to be considered in designing a system. In this paper, we proposed the CCMOS (Clocked CMOS) with fixed frequency and throughput.

The average power consumption using power gating CCMOS is low compared to conventional CMOS logic. The dissipation of power in CCMOS logic can be minimized. The energy consumption by CCMOS logic for various types of D-flip flops and their static and average powers are computed. We compares various types of flip flops in terms of power. From the simulation results, the total power of CMOS and CCMOS are calculated and compared. The circuits have been simulated. It has high speed. It has minimum power consumption compared with all other realizations.


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