

Hybrid Low Power Encoded Multiplier for Montgomery Modular Multiplication and Efficient ECC Processor
Abstract
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References
N. Koblitz, “Elliptic Curve Cryptosystems,” Mathematics of Computation, vol.48, pp.203–209, November 1987.
V. S. Miller, “Use of elliptic curves in cryptography,” in CRYPT0 ‟85, pp.417-426, 1986.
C. Shu, K. Gaj, and T. El-Ghazawi, “Low Latency Elliptic Curve Cryptography Accelerators for NIST Curves over Binary Fields,” FPT 2005 1965, pp. 309-310, 2005.
Satoh and K. Takano, “A Scalable Dual-Field Elliptic Curve Cryptographic Processor,” IEEE Trans. Computers, Vol. 52, No. 4, pp. 449-460, April. 2003.
N. Gura, S.C. Shantz, H. Eberle, S. Gupta, V. Gupta, D. Finchelstein, E.Goupy, and D.Stebila, “An End-to-End Systems Approach to Elliptic Curve Cryptography,” CHES 2002,Lecture Notes in Computer Science 2523, pp. 349-365, 2002.
IEEE 1363, Standard Specifications for Publickey Cryptography, 2000.
NIST, Recommended elliptic curves for federal government use, May 1999. http://csrc.nist.gov/encryption.
Justin Hensley, Anselmo Lastra and Montek Singh,” An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices”, Proceedings of the IEEE International Conference on Computer Design, pp.18-25, 2004.
Sandeep Kumar, Thomas Wollinger, and Christof Paar,” Optimum Digit Serial GF(2m) Multipliers for Curve-Based Cryptography”, IEEE Transactions On Computers, Vol. 55, No.10, pp 1306-1311, October 2006.
S.Saravanan, M.Madheswaran,” Design and Analysis of a Spurious Switching Suppression Technique Equipped Low Power Multiplier with Hybrid Encoding Scheme”, International Journal of Computer Science and Information Security, Vol. 6, No. 3, pp 73-78, 2009.
S.Saravanan, M.Madheswaran,” Design of Hybrid Encoded Booth Multiplier with Reduced Switching Activity Technique and Low Power 0.13μm Adder for DSP Block in Wireless Sensor Node”, Proceeding on IEEE conference on wireless communication and sensor computing , pp:1-6, 2010.
Mark Hamilton, William P. Marnane , Arnaud Tisserand,” A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values” proceeding of the IEEE 21st International Conference on Field Programmable Logic and Applications, pp. 273-276, 2011.
J. Lopez and R. Dahab, “Fast multiplication on elliptic curves over GF(2m) without precomputation”, in Cryptographic Hardware and Embedded Systems (CHES), , vol. 1717 of LNCS, pp. 316–327, Springer-Verlag, Aug. 1999.
Yinan Kong,” Optimizing the Improved Barrett Modular Multipliers for Public-Key Cryptography “, in Proceeding of IEEE Conference on Computational Intelligence and Software Engineering (CISE),pp.1-4, 2010.
H. Rahaman, J. Mathew, B.K.Sikdar, and D. K. Pradhan,” Transition Fault Testability in Bit Parallel Multipliers over GF(2m)”, in Proceeding of 25th IEEE conference on VLSI Test Symposium, pp.422-430, 2007.
Hyejung Kim, Yongsang Kim, and Hoi-Jun Yoo,” A 6.3nJ/op Low Energy 160-bit Modulo-Multiplier for Elliptic Curve Cryptography Processor “, in Proceeding of IEEE International Symposium on Circuits and Systems(ISCAS), pp.3310-3313 ,2008.
http://En.wikipedia.org/wiki/Binary_multiplier.
H. M. Choi, C. P. Hong, and C. H. Kim, “High performance elliptic curve cryptographic processor over GF(2163)”, in Proc. IEEE Int. Symposium on Electronic Design, Test, and Applications (DELTA), Hong Kong, pp. 290–295.Jan. 2008,
Mohammed Benaissa and Wei Ming Lim,” Design of Flexible Elliptic Curve GF(2m) Cryptography Processors “,IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 6, pp . 659- 662, June 2006.
J.-Y. Lai and C.-T. Huang,” High-Performance Architecture for Elliptic Curve Cryptography over Binary Field”, in Proceeding on IEEE international Symposium on circuits and system(ISCAS), pp.3933-3936, 2010.
A.Kaleel Rahuman, G.Athisha, ” Reconfigurable Architecture for Elliptic Curve Cryptography”, in Proceedings of the International Conference on Communication and Computational Intelligence,pp.461-46, December, 2010.
B. Muthukumar[4] Satoh and K. Takano, “A Scalable Dual-Field Elliptic Curve Cryptographic Processor,” IEEE Trans. Computers, Vol. 52, No. 4, pp. 449-460, April. 2003.
N. Gura, S.C. Shantz, H. Eberle, S. Gupta, V. Gupta, D. Finchelstein, E.Goupy, and D.Stebila, “An End-to-End Systems Approach to Elliptic Curve Cryptography,” CHES 2002,Lecture Notes in Computer Science 2523, pp. 349-365, 2002.
IEEE 1363, Standard Specifications for Publickey Cryptography, 2000.
NIST, Recommended elliptic curves for federal government use, May 1999. http://csrc.nist.gov/encryption.
Justin Hensley, Anselmo Lastra and Montek Singh,” An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices”, Proceedings of the IEEE International Conference on Computer Design, pp.18-25, 2004.
Sandeep Kumar, Thomas Wollinger, and Christof Paar,” Optimum Digit Serial GF(2m) Multipliers for Curve-Based Cryptography”, IEEE Transactions On Computers, Vol. 55, No.10, pp 1306-1311, October 2006.
S.Saravanan, M.Madheswaran,” Design and Analysis of a Spurious Switching Suppression Technique Equipped Low Power Multiplier with Hybrid Encoding Scheme”, International Journal of Computer Science and Information Security, Vol. 6, No. 3, pp 73-78, 2009.
S.Saravanan, M.Madheswaran,” Design of Hybrid Encoded Booth Multiplier with Reduced Switching Activity Technique and Low Power 0.13μm Adder for DSP Block in Wireless Sensor Node”, Proceeding on IEEE conference on wireless communication and sensor computing , pp:1-6, 2010.
Mark Hamilton, William P. Marnane , Arnaud Tisserand,” A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values” proceeding of the IEEE 21st International Conference on Field Programmable Logic and Applications, pp. 273-276, 2011.
J. Lopez and R. Dahab, “Fast multiplication on elliptic curves over GF(2m) without precomputation”, in Cryptographic Hardware and Embedded Systems (CHES), , vol. 1717 of LNCS, pp. 316–327, Springer-Verlag, Aug. 1999.
Yinan Kong,” Optimizing the Improved Barrett Modular Multipliers for Public-Key Cryptography “, in Proceeding of IEEE Conference on Computational Intelligence and Software Engineering (CISE),pp.1-4, 2010.
H. Rahaman, J. Mathew, B.K.Sikdar, and D. K. Pradhan,” Transition Fault Testability in Bit Parallel Multipliers over GF(2m)”, in Proceeding of 25th IEEE conference on VLSI Test Symposium, pp.422-430, 2007.
Hyejung Kim, Yongsang Kim, and Hoi-Jun Yoo,” A 6.3nJ/op Low Energy 160-bit Modulo-Multiplier for Elliptic Curve Cryptography Processor “, in Proceeding of IEEE International Symposium on Circuits and Systems(ISCAS), pp.3310-3313 ,2008.
http://En.wikipedia.org/wiki/Binary_multiplier.
H. M. Choi, C. P. Hong, and C. H. Kim, “High performance elliptic curve cryptographic processor over GF(2163)”, in Proc. IEEE Int. Symposium on Electronic Design, Test, and Applications (DELTA), Hong Kong, pp. 290–295.Jan. 2008,
Mohammed Benaissa and Wei Ming Lim,” Design of Flexible Elliptic Curve GF(2m) Cryptography Processors “,IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 6, pp . 659- 662, June 2006.
J.-Y. Lai and C.-T. Huang,” High-Performance Architecture for Elliptic Curve Cryptography over Binary Field”, in Proceeding on IEEE international Symposium on circuits and system(ISCAS), pp.3933-3936, 2010.
A.Kaleel Rahuman, G.Athisha, ” Reconfigurable Architecture for Elliptic Curve Cryptography”, in Proceedings of the International Conference on Communication and Computational Intelligence,pp.461-46, December, 2010.
B. Muthukumar
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