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Hybrid Low Power Encoded Multiplier for Montgomery Modular Multiplication and Efficient ECC Processor

B. Muthukumar, S. Jeevananthan

Abstract


Elliptic Curve Cryptography (ECC) rules communication where the requirements of security, speed, key length and area constraints become main objective such as the portable device. Scalar multiplication becomes the key operation in any ECC, not only because it munches out major time, power and chip area, it is also a fact that the triumph of the Elliptic Curve Encryption Algorithm depends on the difficulty of calculating the multiplication. Hence the type of multiplier and its functional behavior become crux of the ECC architecture. This paper paves a way by developing a ECC architectures over GF(2160), which is bequeathed with three different multipliers namely array multiplier, modified booth multiplier and hybrid low power encoded multiplier. These multipliers are used in the Montgomery scalar multiplication algorithm to perform point addition and point doubling. The proposed ECC processor can perform the 160 bit point multiplication and coordinates conversion with 575mW, 511mW and 373mW in 100 MHz and 19176, 16260 and 8743 LUTs respectively in array multiplier, modified booth multiplier and hybrid multiplier. The architecture is implemented using spartan3E family device XC3S1600E using Modelsim 5.7 and Xilinx 9.2i.

Keywords


Array Multiplier, Elliptic Curve Cryptography, Hybrid Low Power Encoded Multiplier, Montgomery Multiplication Algorithm, Modified Booth Multiplier, Point Double, Point Addition

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References


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NIST, Recommended elliptic curves for federal government use, May 1999. http://csrc.nist.gov/encryption.

Justin Hensley, Anselmo Lastra and Montek Singh,” An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices”, Proceedings of the IEEE International Conference on Computer Design, pp.18-25, 2004.

Sandeep Kumar, Thomas Wollinger, and Christof Paar,” Optimum Digit Serial GF(2m) Multipliers for Curve-Based Cryptography”, IEEE Transactions On Computers, Vol. 55, No.10, pp 1306-1311, October 2006.

S.Saravanan, M.Madheswaran,” Design and Analysis of a Spurious Switching Suppression Technique Equipped Low Power Multiplier with Hybrid Encoding Scheme”, International Journal of Computer Science and Information Security, Vol. 6, No. 3, pp 73-78, 2009.

S.Saravanan, M.Madheswaran,” Design of Hybrid Encoded Booth Multiplier with Reduced Switching Activity Technique and Low Power 0.13μm Adder for DSP Block in Wireless Sensor Node”, Proceeding on IEEE conference on wireless communication and sensor computing , pp:1-6, 2010.

Mark Hamilton, William P. Marnane , Arnaud Tisserand,” A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values” proceeding of the IEEE 21st International Conference on Field Programmable Logic and Applications, pp. 273-276, 2011.

J. Lopez and R. Dahab, “Fast multiplication on elliptic curves over GF(2m) without precomputation”, in Cryptographic Hardware and Embedded Systems (CHES), , vol. 1717 of LNCS, pp. 316–327, Springer-Verlag, Aug. 1999.

Yinan Kong,” Optimizing the Improved Barrett Modular Multipliers for Public-Key Cryptography “, in Proceeding of IEEE Conference on Computational Intelligence and Software Engineering (CISE),pp.1-4, 2010.

H. Rahaman, J. Mathew, B.K.Sikdar, and D. K. Pradhan,” Transition Fault Testability in Bit Parallel Multipliers over GF(2m)”, in Proceeding of 25th IEEE conference on VLSI Test Symposium, pp.422-430, 2007.

Hyejung Kim, Yongsang Kim, and Hoi-Jun Yoo,” A 6.3nJ/op Low Energy 160-bit Modulo-Multiplier for Elliptic Curve Cryptography Processor “, in Proceeding of IEEE International Symposium on Circuits and Systems(ISCAS), pp.3310-3313 ,2008.

http://En.wikipedia.org/wiki/Binary_multiplier.

H. M. Choi, C. P. Hong, and C. H. Kim, “High performance elliptic curve cryptographic processor over GF(2163)”, in Proc. IEEE Int. Symposium on Electronic Design, Test, and Applications (DELTA), Hong Kong, pp. 290–295.Jan. 2008,

Mohammed Benaissa and Wei Ming Lim,” Design of Flexible Elliptic Curve GF(2m) Cryptography Processors “,IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 6, pp . 659- 662, June 2006.

J.-Y. Lai and C.-T. Huang,” High-Performance Architecture for Elliptic Curve Cryptography over Binary Field”, in Proceeding on IEEE international Symposium on circuits and system(ISCAS), pp.3933-3936, 2010.

A.Kaleel Rahuman, G.Athisha, ” Reconfigurable Architecture for Elliptic Curve Cryptography”, in Proceedings of the International Conference on Communication and Computational Intelligence,pp.461-46, December, 2010.

B. Muthukumar


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