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FPGA Implementation of Multi Layer Perceptron Neural Network for Signal Processing

A. Thilagavathy, K. Vijaya Kanth

Abstract


Artificial Neural Networks support their processing capabilities in a parallel architecture. It is widely used in pattern recognition, system identification and control problems. Multilayer Perceptron is an artificial neural network with one or more hidden layers. This paper presents the digital implementation of multi layer perceptron neuron network using FPGA (Field Programmable Gate Array) for pattern recognition. If the pattern matches with the original then process continued else it is rejected. This network was implemented by using three types of non linear activation function: hardlims, satlins and tansig. A neural network was implemented by using VHDL hardware description Language codes and XC3S250E-PQ 208 Xilinx FPGA device. The results obtained with Xilinx Foundation 9.2i software are presented. The results are analyzed by using device utilization and time delay.


Keywords


FPGA, Multi Layer Perceptron, Neuron Plan Approximation, Sigmoid Activation

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References


Rafid Ahmed Khalil Sa’ad Ahmed AI-Kazzaz “Digital Hardware implementation of Artificial Neurons models using FPGA” , Springer U.S.,2012.

Neeraj Chasta , Sarita Chouhan and Yogesh Kumar, “ Analog VLSI implementation of neural network architecture for signal processing” VLSICS., Vol.3.no.12,2012.

Manish Panicker, C.Babu, “Efficient FPGA Implementation of Sigmoid and Bipolar Sigmoid Activation Functions” IOSR Journal of Engineering 2012.

R.Omondi, C. Rajapakse, “FPGA Implementation of Neural Networks”, Springer U.S., 2006.

O. Maischberger ,V. Salapura , “ A Fast FPGA Implementation of a General Purpose Neuron”, Technical University , Institute of in formatik , Austria , 2006.

Hiroomi Hikawa , “A Digital Hardware Pulse-Model Neuron With Piecewise Linear Activation Function,” IEEE Trans.Neural Networks, vol.14,no.5,pp.1028-1037,Sept.2003

M. Banuelos Sauced, et. al., “Implementation of neuron model using FPGAs”. Journal of Applied Research and Technology ISSN: 1665- 6423, vol. 3 (10), 2003, pp. 248-255.

Parasovic A., latinovic I . , “A Neural Network FPGA Implementation” . IEEE. 5th seminar on Neural Network Application in Electrical Engineering , September 2000 , PP117 – 120

Ranjeet Ranade & Sanjay Bhandari & A.N. Chandorkar “VLSI Implementation of Artificial Neural Digital Multiplier and Adder” pp.318-319.

Roy Ludvig Sigvartsen, An Analog Neural Network with On-Chip Learning Thesis Department of informatics, University of Oslo, 1994.

D. Nguyen a and B. Wid row, Improving the learning speed of 2-layer neural network by choosing initial values of the adaptive weights, IEEE First International Joint Conference on Neural Networks , 3, 21–26, (1990).

S. Orcioni G. Biagetti, M. Conti, “A mixed signal fuzzy controller using current model circuits, “ Analog Integrated Circuits Process. 38, 2004 , pp.215-231.

Sahin, I. Koyuncu “Design and Implementation of Neural Networks Neurons with RadBas, LogSig, and TanSig Activation Functions on FPGA”.

Nirmaladevi M., Mohankumar N., Arumugam S. Modeling and Analysis of Neuro–Genetic Hybrid System on FPGA // Electronics and Electrical Engineering. – Kaunas: Technologija, 2009. – No. 8(96). – P. 69–74.

Reyneri L. M. Implementation Issues of Neuro–Fuzzy Hardware: Going Toward HW/SW Codesign // IEEE Transactions on Neural Networks, 2003. –Vol. 14. – No. 1.

Paukštaitis V., Dosinas A. Pulsed Neural Networks for Image Processing // Electronics and Electrical Engineering. – Kaunas: Technologija, 2009. – No. 7(95). – P. 15–20.

Rutka G. Prediction Accuracy of Neural Network Models // Electronics and Electrical Engineering. – Kaunas: Technologija, 2008. – No. 3(83). – P. 29–32.

Raudonis V., Narvydas G., Simutis R. A Classification of Flash Evoked Potentials based on Artificial Neural Network // Electronics and Electrical Engineering. – Kaunas: Technologija, 2008. – No. 1(81). – P. 31–36.

Juang J. G., Chien L. H.,Lin F. Automatic Landing Control System Design Using Adaptive Neural Network and Its Hardware Realization // IEEE System Journal, 2011. – Vol. 5.– No. 2.

Yonggang W., Junwei D., Zhonghui Z., Yang Y., Lijun Z., Bruyndonckx P. FPGA Based Electronics for PET Detector Modules With Neural Network Position Estimators // IEEE Trans. on Nuclear Science, 2011. – Vol. 58. – No. 1.

Himavathi S., Anitha D., Muthuramalingam A. Feedforward Neural Network Implementation in FPGA Using Layer Multiplexing for Effective Resource Utilization // IEEE Trans. on Neural Networks, 2007. –Vol. 18. – No. 3.

Sahin I. A 32–bit floating–point module design for 3D graphic transformations. – 2010. – Vol. 5(20). – 3070 p.

Gomperts A., Ukil A., Zurfluh F. Development and Implementation of Parameterized FPGA–Based General Purpose Neural Networks for Online Applications // IEEE Trans. on Industrial Informatics, 2011. – Vol. 7. – No. 1.

E. Vittoz, et al.,” The design of high performance analog circuits on digital CMOS chips,” IEEE J. Solid State Circuit 20, 1985, pp.657-665


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