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Improved Cyber Security by Hardware Acceleration of Scalable Encryption Algorithm in OpenSSL

A. Thiruneelakandan, N. Hemavathy

Abstract


Providing improved Information Security to the rapidly developing Cybernet System has become a vital factor in the present technically networked world. The information security concept has become a more complicated subject when next generation system requirements and real time computation speed are considered. In order to solve these issues, lots of research and development activities are carried out and cryptography has been a very important part of any communication system in the recent years. Cryptographic algorithms fulfil specific information security requirements such as data integrity, confidentiality and authenticity. This work proposes an FPGA-based VLSI Crypto-System, integrating hardware that accelerates the cryptographic algorithms used in the SSL/TLS protocol. SSL v3 and TLS v1 protocol is deployed in the proposed system powered with a Nios-2 soft-core processor. Key cipher functions used in SSL-driven connection is Scalable Encryption Algorithm (SEA). This algorithm is accelerated in the VLSI Crypto-System that is on an Altera Cyclone III FPGA DE2 development board. The experimental results shows that, by hardware acceleration of SEA cryptographic algorithm, the performance of VLSI Crypto-System has increased in terms of speed, optimized area and enhanced strength of network security for the target Cybernet application.

Keywords


Cryptographic Algorithm, Hardware Accelerator, SSL/TLS Protocol, C to H Compiler, VLSI Crypto – System, Altera Cyclone III FPGA DE2.

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