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PCI Configuration based Data Security Architecture and Co-Design Techniques
Abstract
The recovery of intentional/ unintentional
modification of data is conventionally done by creating a
backup/copy of data prior to its modification. Alternately, In this paper, the data recovery process is performed by contextually switching the semaphores to control the system resources. The designed hardware is placed in the PCI slot between the CPU and lower-level peripherals. A binary semaphore controls the data flow between the designed hardware and the CPU, whereas a mutually
exclusive (context-switching) semaphore controls the data flow
between the designed hardware and lower-level peripherals. The semaphore management mechanisms are moved from the application to the physical and data-link communication layers. A fully distributed management scheme is implemented, and there is no need to place the semaphore control structures on a particular node in the
network. The existing version of the selected data file is copied and directed to a non-readable area of the secondary storage. This ensures retrieval of the former contents of the data file via Linked Link concept if the current modification is not authenticated.
Keywords
References
Ilgun, K., “USTAT: A Real-time Intrusion Detection System for UNIX”,
in proceedings of the IEEE Symposium on Research in Security and
Privacy, pp. 16-28, 1993.
T. Yamauchi et al., “Fully Self-timing Data-Bus Architecture for 64-Mb
DRAMs”, IEICE TRANS. ELECTRON., VOL. E78-C, NO.7, pp. 885-
, 1995.
Peter Petrov and Alex Orailoglu, “Towards effective embedded
processors in codesigns: Customizable partitioned caches”, in
proceedings of the 9th International Symposium on Hardware/Software
Codesign, pages 79-84, Copenhagen, Denmark, 2001.
W.T. Shiue and C. Chakrabarti, “Memory exploration for low power,
embedded systems”, in Design Automation Conference, pages 140-145,
New York, 1999.
W. Wolf and M. Kandemir, “Memory system optimization of embedded
software”, in proceedings of the IEEE, 91(1), January 2003.
A. Asaduzzaman and I. Mahgoub, “Cache Optimization for Embedded
Systems Running”, AVC Video Decoder, AICCSA06 IEEE
International Conference, UAE, pages 665-672, 2006.
S. Mohanty, V.K. Prasanna, “Design of High-Performance Embedded
System using Model Integrated Computing”, 10th IEEE Real-Time and
Embedded Technology and Applications Symposium (RTAS-2004),
P.R. Panda, F. Catthoor, P.G. Kjeldsberg, “Data and Memory
Optimization Techniques for Embedded Systems”, ACM Transactions
on Design Automation of Electronic Systems, Vol. 8, No. 2, pages 149-
, 2001.
F. Ricci, L. T. Clark, T. Beatty, W. Yu, A. Bashmakov, S. Demmons, E.
Fox, J. Miller, M. Biyani, J. Haigh, "A 1.5 GHz 90 nm embedded
microprocessor core," Digest of Technical Papers. Symposium on VLSI
Circuits, pp. 12-15, June 2005.
S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E.
Alon, M. Horowitz, "The implementation of a 2-core, multi-threaded
itanium family processor," Journal of Solid-State Circuits,vol. 41, issue
, pp. 197-209, Jan. 2006.
M. Sheets, F. Burghardt, T. Karalar, J. Ammer, Y. Chee, J. Rabaey, "A
Power-Managed Protocol Processor for Wireless Sensor Networks,"
Digest of Technical Papers. Symposium on VLSI Circuits, pp. 212-213,
June, 2006.
B. H. Calhoun, A. Chandrakasan, "A 256kb sub-threshold SRAM in
nm CMOS," IEEE International Solid-State Circuits Conference, pp.
, Feb 2005.
Z. Guo, S. Balasubramanian, R. Zlatanovici, T. J. King, B. Nikolic,
"FinFET-based SRAM design," International Symposium on Low
Power Electronics and Design, pp. 2-7, Aug. 2005.
K. Zhang, et al., "SRAM design on 65-nm CMOS technology with
dynamic sleep transistor for leakage reduction," IEEE Journal of Solid-
State Circuits, vol. 40, issue 4, pp. 895-901, April 2005.
C. H. Kim, J. Kim, I. Chang, and K. Roy, "PVT-Aware leakage
reduction for on-die caches with improved read stability", IEEE Journal
of Solid-State Circuits, vol. 41, no. 1, pp. 170-178, Jan. 2006.
M. Khellah, D. Somasekhar, Y. Ye, N. S. Kim, J. Howard, G. Ruhl, M.
Sunna, J. Tschanz, N. Borkar,F. Hamzaoglu, G. Pandya, A. Farhang, K.
Zhang, V. De, "A 256-Kb Dual-VCC SRAM Building Block in 65-nm
CMOS Process With Actively Clamped Sleep Transistor," IEEE Journal
of Solid-State Circuits, vol. 42, issue 1, pp. 233-242, Jan. 2007.
M. Agostinelli et al., "Erratic fluctuations of SRAM cache vmin at the
nm process technology node," IEEE International Electron Devices
Meeting, pp. 655–658, Dec 2005.
K. Takeda, H. Ikeda, Y. Hagihara, M. Nomura and H. Kobatake,
"Redefinition of write margin for next-generation SRAM and writemargin
monitoring circuit", International Solid-State Circuits
Conference, pp. 630-631, Feb 2006.
A. Kumar, et al., "Fundamental bounds on power reduction during
SRAM standby data-retention", in press, IEEE International Symposium
on Circuits and Systems, 2007.
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