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Self Healing Reconfigurable Unit for Error Detection and Correction in Networks

S.P. Anandaraj, Dr.S. Ravi, Dr.V. Chanthan


This paper discusses an embedded reconfigurable architecture to perform error detection and correction in the physical layer in OSI network. Specifically, the three popular self-healing architectures namely, Cyclic Redundancy Check (CRC), Longitudinal redundancy Check (LRC) and Character Stuffing; are implemented in the field programmable gate array (FPGA). Performance metrics are used to assess the feasibility of the designed reconfigurable architecture. Additionally, to justify the hypothesis of single faults and avoid accumulation of undetected errors in FPGAs and memory systems, scrubbing is used. Relatively little research has been done on designing fault-tolerant reconfigurable fine-grained systems like FPGAs which are complete (i.e. including error recovery). In case of a fault occurrence the correct operation of the affected module must be restored and/or the current state of the circuit coherently re-established. The proposed system shall serve as a core for future embedded server with an ability to perform error detection and correction.


FPGA, Physical Layer, Error Detection and Correction, CRC, LRC, Character Stuffing.

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