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Design of ADC for ECG Applications using 0.18μM CMOS Technology

D. Jackuline Moni, H. Victor Du John

Abstract


The necessity of wireless ECG transmission is increasing in day to day life. To transmit the ECG signal, the conversion of analog ECG to digital is more important and the same is achieved using analog to digital converters. This paper concentrates on the design of charge redistribution successive approximation type ADC in 180nm CMOS technology. This analog to digital converter is designed for the use of wireless medical ECG applications with the sampling rate of 5KS/s and 10 bit resolution for the input range of 10mv, since the ECG signal having very less amplitude. The principle used in this paper is charge redistribution adiabatic charging type digital to analog converter in the ADC circuit which consumes very less power. The regenerative comparator in the ADC also reduces the power consumption of the circuit. The digital output is collected from the SAR register which is constructed using flip-flops which can act as a ring counter. The SAR register gets the input from the regenerative comparator which is the error signal of the comparator from charge redistribution DAC and S&H. The whole circuit is driven by the clock input. This ADC will be more suitable for low frequency medical applications consuming 8.3μW at 1.2V supply voltage. Noise analysis is done and jitter noise is reduced.

Keywords


Charge Redistribution, Jitter Noise, Regenerative, SAR-ADC.

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References


M. Van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink and B. Nauta, ―A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,‖ ISSCC Dig. Tech. Papers, Feb. 2008

M. Van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink and B. Nauta, A 10-bit Charge-Redistribution ADC Consuming 1.9μW at 1 MS/s.

Li Yu, Jin-yong Zhang, Lei Wang, Jian-guo Lu, A 12-bit Fully Differential SAR ADC with Dynamic Latch Comparator for Portable Physiological Monitoring Applications

Jens Sauerbrey, Doris Schmitt-Landsiedel, Roland Thewes, ―A 0.5V, 1μW Successive Approximation ADC‖, IEEE Journal of Solid State Circuit, IEEE 2002.

Raouf Khalil, Andrii Dudka, Dimitri Galayko, Ramy Iskander, Design and Modeling of a Successive Approximation ADC for the Electrostatic Harvester of Vibration Energy

The operation of the SAR-ADC based on charge redistribution, By Thomas Kugelstadt, 2005 Texas Instruments.

Phillip DAllen.,Douglas R Holberg., CMOS Analog circuit design second edition Oxford university press.

Aniruddha C. Kailuke, Vrushali G. Nasre, M.Shojaei-Baghini, Rajendra.D.Kanphade, Design of Low Power Integrated SAR-ADC in 0.18μm Mixed-Mode CMOS Process.

Fan Hua, Wei Qi, Kobenge Sekedi Bomeh, Yin Xiumei,and Yang Huazhong, (Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China) An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB.

Alberto Rodríguez-Pérez, Manuel Delgado-Restituto and Fernando, MedeiroInstitute of Microelectronics of Seville, Power Efficient ADCs

MAXIM Application note 1080 Understanding SAR ADCs Mar 01, 2001.

James L. McCreary, student member, IEEE, and Paul r. Gray, member, IEEE, all-mos charge redistribution analog-to-digital conversion techniques—part-1.

Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U,A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS.

Daniel Schinkel, Eisse Mensink, Eric Klumperink, Ed van Tuijl, Bram Nauta, A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time.

Brian P. Ginsburg and Anantha P. Chandrakasan Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology, Cambridge, An Energy-Efficient Charge Recycling Approach for a SAR Converter With Capacitive DAC


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