Design of Low Power SRAM by Reducing Wordline Pulsewidth

Abstract

Power dissipation is recognized as a critical parameter in modern VLSI design field. There is a strong demand for SRAM with lower power consumption while achieving high performance and high density. In the presence of large process variations, SRAMs are expected to consume larger power to ensure correct read operations and meet yield targets. SRAM array switching power consumption is considered one of the largest components of power in high-density memories. For normal operating conditions, array power consumption is more than 60% of read power. Therefore, it is important to reduce the array switching due to its strong impact on the memory‘s total power as well as the SoC‘s power. Several circuit techniques have been used to reduce the SRAM array switching power consumption by reducing the WL pulse width. A new architecture that significantly reduces the array switching power for SRAM has been used. The architecture combines built-in self-test and digitally controlled delay elements to reduce the word line pulse width for memories while ensuring correct read operations, hence reducing the switching power.