Energy Minimization of Scratchpad Memory Using Optimal SPM Mapping and Memory Power-Down Scheduling

Abstract

The memory subsystem are consumes 50%-75% of the total energy in an embedded Systems. Moreover, there exists a large potential for optimizing the energy consumption of the memory subsystem. Scratchpad Memories are widely employed in embedded systems as an alternative to caches because they achieve comparable performance with higher power efficiency. Here, Optimal SPM Mapping and Memory Power-Down techniques are used for minimize the total energy of the SPM. SPM mapping simply targets the minimum number of accesses to the main memory, i.e., active power. A global optimization should explicitly take into account memory access energy, leakage energy, and power- down/up energy penalty, to define the Optimal SPM mapping and optimal memory power-down scheduling for minimizing the total energy in the memory sub-system. Synthesis results based on 1.32V CMOS standard-cell library shows that the proposed SPM reduces the power consumption by 25-30%.