Open Access Open Access  Restricted Access Subscription or Fee Access

Device Modeling and Transistor Stacking for High Speed with Low Power Requirements Using Double Gate Devices

D. Jackuline Moni, B. Suresh, R. Malarkodi

Abstract


This paper describes the device characteristics verification and biasing analysis of Silicon on Insulator (SOI) devices with single gate and double gate in comparison with bulk MOSFET. Improvement in threshold voltage controllability and variability has been observed for these devices. One of the leading double gate devices, FinFET is analyzed over different parameter variations and with back biasing techniques. Wide threshold voltage controllability of the FinFET device in comparison with all other devices is justified. The performance of independently gated four–terminal FinFETs with symmetric gate-oxide thickness (tox1=tox2=0.5nm) and the same kind FinFET with asymmetric gate-oxide thickness whose front gate-oxide tox1=0.5nm and back gate-oxide tox2=5nm, has been successfully analyzed. A comparison between symmetric and asymmetric gate work function has been analyzed. Also the gate oxide materials are changed and the response for High-K materials is analyzed and compared with the conventional devices. Some of the peculiar characteristics exhibited by the device for the fin width variation when controlled in single gate (SG) and independent gate (IG) modes have been proposed here.

Keywords


FinFET, SOI, Single Gate, Double Gate, High k

Full Text:

PDF

References


M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein, “Scaling, power, and the future of CMOS,” in IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., Dec. 2005, p. 9.

Jean-Pierre Colinge, FinFETs and other Multi-Gate Transistors, Springer 2008.

M. Masahara et al., “Demonstration analysis and device design considerations for independent DG MOSFETs,” IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 2046–2053, Sep. 2005.

D. Fried, E. Nowak, J. Kedzierski, J. Duster, and K. Komegay, “A fin-type independent-double-gate NFET,” in Proc. Device Res. Conf., Jun. 2003, pp. 45–46.

R. T. Cakici and K. Roy, “Analysis of options in double-gate MOS technology: A circuit perspective,” IEEE Trans. Electron Devices, vol.54, no.12, pp. 3361–3368, Dec. 2007.

S. Narendra, V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan, “Full chip sub-threshold leakage power prediction and reduction techniques for sub-0.18-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39,no. 3, pp. 501–510, Mar. 2004.

Matteo Agostinelli, Massimo Alioto, David Esseni, and Luca Selmi, “Leakage–Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis with Bulk Technology” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 232–245, Feb. 2010

W. Zhang, J. Fossum, L. Mathew, and Y. Du, “Physical insights regarding design and performance of independent-gate FinFETs,” IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2198–2206, Oct.2005.

Z. Lu and J. Fossum, “Short-channel effects in independent-gate Fin-FETs,” IEEE Electron Device Lett., vol. 28, no. 2, pp. 145–147, Feb. 2007.

K. von Arnim, “Efficiency of body biasing in 90-nm CMOS for low power digital circuits,” in Proc. 30th ESSCIRC, Sep. 2004, pp. 175–178.

Yongxun Li et al., “Co-integration of high-performance tied-gate three-terminal FinFETs and variable threshold-voltage independent-gate four-terminal FinFETs with asymmetric gate-oxide thicknesses.” IEEE Electron Device Lett. vol. 28, no. 6, pp 517-519, June 2007.

Behzad Razavi, Design of Analog CMOS Integrated circuits, Tata McGraw-Hill, Edition 2002.

Kerry et al., High speed CMOS Design Styles, Kluwer Academic Publishers 2001.


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.