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Design and Simulation of Contention Free Clos Network using VHDL

S. Rajeshwari, R. Bharathi

Abstract


Clos network, a family of multistage networks, is applied to build scalable commercial multiprocessors with thousands of nodes in macro systems. An MPSoC is a system on- chip a VLSI system that incorporates most or all the components necessary for an application that uses multiple programmable processors as system components. This paper presents the design and simulation of clos network that provides the contention free permutation in multiprocessor system on chip (MPSoC).The proposed clos network employs an ID matching scheme with pipelined circuit switching and dynamic path setup scheme based on Exhausted Profitable backtracking (EPB) under a multistage network topology. Due to the pre-configured circuit-switched data paths, applying a source-synchronous data transfer scheme is feasible. The ID matching scheme offers a contention free routing from unauthorized users. The pipelined circuit switching approach offers a guarantee of permutated data. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. The dynamic path setup scheme enables run time path arrangement for arbitrary traffic permutation.

Keywords


ID Matching, Multistage Interconnection Network, On Chip Permutation Network, Pipelined Circuit Switching, Traffic Permutation.

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