Exploiting of Way Tag Information to Improve Energy-Efficient in L2 Cache Architecture

Abstract

Caches are the main structures in modern microprocessors but they are harmed to the transient errors. Implementing same tag bits to increase error protection capability of the tag bits in the caches. When data are access from the main memory, then it checks if equivalent cache lines also contain the same tag bits of the data fetched, these same tag bit value is stored in the sti location. When an error is identified in the tag bits, the same tag bit information is used to replace the error in the tag bits. In this project, proposed a way-tagged cache to increase the energy efficiency of write-through caches. The way tags technique of L2 cache in L1 cache through read operations the way tag will enables the L2 cache to process in an corresponding manner during write hits, which access for the most of L2 cache accesses. This will leads to energy reduction in cache architecture without performance degradation. Future work is directed towards this technique to extending other levels of cache hierarchy and improve the energy consumption of other cache operations.