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Low Power Test Vector Subset Generation
Abstract
The test of Integrated circuits by random patterns is very attractive, since no expensive test pattern generation is necessary and tests can be applied with a selt test technique or externally using LFSR. Weighted pseudorandom built-in self-test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. A method for accumulator based low hardware 3-weight pattern generation is described. The main advantages of the method described over existing methods are: 1) only three easily generated weights-0, 1, 0.5 are used.2)As accumulators are commonly used in current VLSI chips, this scheme can efficiently drive down the hardware of BIST pattern generation. An experimental result shows that the proposed BIST scheme can attain 100% fault coverage for all of the benchmark circuits and an average reduction of 73.5% in hardware requirement compared to two previous methodologies.
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References
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