Email this article 
Open Access
Subscription or Fee Access
Fixed Width Booth Multiplier based on PEB Circuit
Abstract
A probabilistic estimation bias (PEB) circuit for a
fixed-width two’s complement Booth multiplier is proposed for Low Power and High accuracy. The proposed PEB circuit is derived from theoretical computation, instead of exhaustive simulations and heuristic compensation strategies that tend to introduce curve-fitting errors(interpolation) and exponential-grown simulation time. Consequently, the proposed PEB circuit provides a smaller area and a
lower truncation error compared with existing works such as posttruncation and pre- truncation methodologies in Booth Multiplication. Implemented in an 8 × 8 2-D discrete cosine transform (DCT) core, the DCT core using the proposed PEB Booth multiplier improves the
peak signal-to-noise ratio by 17 dB with only a 2% area penalty compared with the direct-truncated method. This PEB circuit also provides extensive applications in digital designs. PEB circuit are more easier to design and can achieve good simulation time in doing computations in higher order bits.
Keywords
References
J. P. Wang, S. R. Kuang, and S. C. Liang, “High-accuracy fixedwidth
modified Booth multipliers for lossy applications,” IEEE Trans.Very
Large Scale Integr. (VLSI) Syst., vol. 19, no. 1, pp. 52–60, Jan. 2011.
M. J. Schulte and E. E. Swartzlander, Jr., “Truncated multiplication with
correction constant,” in VLSI Symp. Tech. Dig., 1993, pp. 388–396.
S. S. Kidambi, F. El-Guibaly, and A. Antoniou, “Area-efficient
multipliers for digital signal processing applications,” IEEE Trans.
Circuits Syst. II,Analog Digit. Signal Process, vol. 43, no. 2, pp. 90–95,
Feb. 1996.
J. M. Jou, S. R. Kuang, and R. D. Chen, “Design of lower-error
fixedwidth multipliers for DSP applications,” IEEE Trans. Circuits Syst.
II,Analog Digit. Signal Process, vol. 46, no. 6, pp. 836–842, Jun. 1999.
L. D. Van, S. S. Wang, and W. S. Feng, “Design of the lower-error
fixedwidth multiplier and its application,” IEEE Trans. Circuits Syst. II,
Analog Digit. Signal Process, vol. 47, no. 10, pp. 1112–1118, Oct. 2000.
L. D. Van and C. C. Yang, “Generalized low-error area-efficient
fixedwidth multipliers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.
,no. 8, pp. 1608–1619, Aug. 2005.
Y. C. Liao, H. C. Chang, and C. W. Liu, “Carry estimation for two’s
complement fixed-width multipliers,” in Proc. IEEE Workshop on
SignalProcess. Syst. Design Implementation, 2006, pp. 345–350.
N. Petra, D. D. Caro, V. Garofalo, E. Napoli, and A. G. M. Strollo,
“Truncated binary multipliers with variable correction and minimum
mean square error,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57,
no. 6, pp. 1312–1325, Jun. 2010.
S. J. Jou, M. H. Tsai, and Y. L. Tsao, “Low-error reduced-width Booth
multipliers for DSP applications,” IEEE Trans. Circuits Syst. I, Fundam.
Theory Appl., vol. 50, no. 11, pp. 1470–1474, Nov. 2003.
K. J. Cho, K. C. Lee, J. G. Chung, and K. K. Parhi, “Design of low-error
fixed-width modified Booth multiplier,” IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 12, no. 5, pp. 522–531, May 2004.
T. B. Juang and S. F. Hsiao, “Low-error carry-free fixed-width
multipliers with low-cost compensation circuits,” IEEE Trans. Circuits
Syst. II, Exp.Briefs, vol. 52, no. 6, pp. 299–303, Jun. 2005.
K. K. Parhi, J. G. Chung, K. C. Lee, and K. J. Cho, “Low-error fixedwidth
modified Booth multiplier,” U.S. Patent 7 334 200, Feb. 19, 2008.
H. A. Huang, Y. C. Liao, and H. C. Chang, “A self-compensation
fixedwidth Booth multiplier and its 128-point FFT applications,” in
Proc. IEEE ISCAS, 2006, pp. 3538–3541.
M. A. Song, L. D. Van, and S. Y. Kuo, “Adaptive low-error fixed-width
Booth multipliers,” IEICE Trans. Fundam., vol. E90-A, no. 6, pp. 1180–
, Jun. 2007.
Y. C. Lim, “Single-precision multiplier with reduced circuit complexity
for signal processing applications,” IEEE Trans. Comput., vol. 41, no.
, pp. 1333–1336, Oct. 1992
B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs..
Oxford, U.K.: Oxford Univ. Press, 2000.
S. C. Hsia and S. H. Wang, “Shift-register-based data transposition for
cost-effective discrete cosine transform,” IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 15, no. 6, pp. 725–728, Jun. 2007.
Refbacks
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.