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Simulation of Nanoscale Gate Length with Composite Channel In0.7Ga0.3As/InAs/In0.7Ga0.3As HEMT using Sentaurus TCAD

V. Balavignesh, P. Anandan

Abstract


The aim of this work is to investigate the nanometer-gate In0.7Ga0.3As/InAs/In0.7Ga0.3 As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250oC, the device exhibited a high gm value at Vd , the current-gain cutoff frequency fT was increased from 390 to 494 GHz, and the gate-delay time was decreased at supply voltage of 0.6 V. This is the highest fT achieved for nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.


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Chien-I Kuo, Heng-Tung Hsu, Edward Yi Chang, Chia-Yuan Chang,Yasuyuki Miyamoto, SumanDatta, Marko Radosavljevic,Guo-Wei Huang, and Ching-Ting Lee,“RF and Logic Performance Improvement ofIn0.7Ga0.3As/InAs/In0.7Ga0.3As Composite-Channel HEMT Using Gate-Sinking Technology,”IEEE.,vol 29, no. 4, pp. 290-293, April 2008.

R. Chau, S. Datta, and A. Majumdar, “Opportunities and challenges of III–V nano electronics for future high-speed, low-power logic applications,” in Proc. IEEE CSIC Dig., pp. 17–20, Nov. 2005.

Chien-Ying Wu, Heng-Tung Hsu, Chien-I Kuo, Chang, Edward Yi, Yu-Lin Chen, “Evaluation of RF and logic performance for 40 nm InAs/InGaAs composite channel HEMTs for high-speed and low-voltage applications,” IEEE ., vol. 25, no. 4, pp. 1–4,Dec. 2008.

L. H.Chu, E. Y.Chang, L.Chang, Y. H.Wu, S. H.Chen, H. T.Hsu, T. L.Lee, Y. C.Lien, and C. Y.Chang, “Effect of gate sinking on the device performance of the InGaP/AlGaAs/InGaAs enhancement- mode PHEMT,” IEEE Electron Device Lett., vol. 28, no. 2, pp. 82–85, Feb. 2007.

K. Shinohara, Y. Yamashita, A. Endoh, K. Hikosaka, T. Matsui, T. Mimura, and S. Hiyamizu, “Extremely high-speed lattice-matched InGaAs/InAlAs high electron mobility transistors with 472 GHz cut- off frequency,” Jpn. J. Appl. Phys., vol. 41, no. 4B, pp. L437–L439, Apr. 2002.

Y. Yamashita, A. Endoh, K. Shinohra, K. Hikosaka, T. Matsui, S. Hiyamizu, and T. Mimura, “Pseudomorphic In0.52Al0.48As/ In0.7Ga0.3As HEMTs with an ultrahigh fT of 562 GHz,” IEEE Electron Device Lett., vol. 23, no. 10, pp. 573–575, Oct. 2002.

D. H. Kim, J. A. Alamo, J. H. Lee, and K. S. Seo, “Performance evaluation of 50 nm In0.7Ga0.3As HEMTs for beyond-CMOS logic applications,” in IEDM Tech. Dig., pp. 767–770, Dec 2005.

K. Shinohara, Y. Yamashita, A. Endoh, I. Watanabe, K. Hikosaka, T. Matsui, T. Mimura, and S. Hiyamizu, “547 GHz ft In0.7Ga0.3As/ In0.52Al0.48As HEMTs with reduced source and drain resistance,” IEEE Electron Device Lett., vol. 25, no. 5, pp. 241–243, May 2004.

K. J. Chen, T. Enoki, K. Arai, and M. Yamamoto, “High-performance InP-based enhancement-mode HEMTs using non-alloyed ohmic contacts and Pt-based buried-gate technologies,” IEEE Trans. Electron Devices, vol. 43, no. 2, pp. 252–257, Feb. 1996.

T. Akazaki, K. Arai, T. Enoki, and Y. Ishii, “Improved InAlAs/InGaAs HEMT characteristics by inserting an InAs layer into the InGaAs channel,” IEEE Electron Device Lett., vol. 13, no. 6, pp. 325–327, Jun. 1992.

R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalierous, A. Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking nanotechnology for high-performance and low-power logic transistor applications,” IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 153–158, Mar. 2005.

Y. Yamashita, A. Endoh, K. Shinohara, M. Higashiwaki, K. Hikosaka, T. Mimura, S. Hiyamizu, and T. Matsui, “Ultra-short 25 nm gate lattice match InAlAs/InGaAs HEMTs within the range of 400 GHz cut off frequency,” IEEE Electron Device Lett., vol. 22, no. 8, pp. 367–369, Aug. 2001.

G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, “A new method for determining the FET small-signal equivalent circuit,” IEEE Trans. Microw. Theory Tech., vol. 36, no. 7, pp. 1151–1159, Jul. 1988.

S. Kim, I. Adesida, and H. Hwang, “Measurements of the thermally induced nanometer-scale diffusion depth of Pt/Ti/Pt/Au gate metallization on InAlAs/InGaAs high-electron mobility transistors,” Appl. Phys. Lett., vol. 87, no. 23, p. 232102, Dec. 2005.

J. Guo, A. Javey, H. Dai, and M. Lundstrom, “Performance analysis and design optimization of near ballistic carbon nano tube field effect transistors,” in IEDM Tech. Dig., 2004, pp. 703–706.

N. Harada, S. Kuroda, T. Katakami, K. Hikosaka, T. Mimura, and M. Abe, “Pt-based gate enhancement-mode InAlAs/InGaAs HEMTs for large- scale integration,” in Proc. 3rd Int. Conf. InP Related Mater., 1991, pp. 377–380.


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