Design of 128 QAM Modulator Using Clock Gating Technique

Abstract

Future Wireless communication systems have to be designed to integrate features such as high data rates, high quality of service and multimedia in the existing communication framework. So modulation techniques that conserve bandwidth are developed using QAM (Quadrature amplitude modulation). In this paper the design of 128-QAM modulator is presented. The RTL code is written in Verilog-HDL and simulated in Xilinx. The power optimization technique i.e. clock gating was carried out for the modulator. Rectangular constellation is used to map the input bits for ease of implementation. It is then mixed with the carrier wave and transmitted. An external memory is used in the design to facilitate low power consumption. The multiplier is disabled after one clock cycle of computation and the data is then retrieved through the memory till the next input arrives. By using clock gating technique, the power is reduced. It is evident from the modified design that by controlling the clock of each sub module, the dynamic power reduced significantly. By incorporating the external memory, the power consumption was reduced by 40%.