Design of a Low Noise Correlated Double Sampled Switched Capacitor Amplifier in Submicron Technology

Abstract

Switched capacitor readout is the most widely used architecture for capacitive sensing. Capacitive sensing is based on charge-voltage relationship, the same foundation on which the SC circuits operate. SC circuit provides a virtual ground and robust dc biasing at the sensing node so that the sensed signal is insensitive to parasitic capacitance and undesirable charging. In switched capacitor circuits, the sense and reference capacitors are charged with opposite polarities and a packet of charge proportional to the capacitance difference is integrated on the input feedback capacitor. In this paper, the switched capacitor technique is incorporated into a simple inverting amplifier to study its significance in submicron IC technology. Analysis on the design constraints required for SC circuits is studied in the paper. Switched capacitor readout front end circuit uses correlated double sampling technique for finite gain, noise reduction and offset cancellation. Simulations are done using 180nm level49 library with the supply tied at 5V. Circuit achieves a noise reduction of more than 50% and a significant reduction in area is observed.