Design of Low Power and High Speed Reversible Multiplier

Abstract

Reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing etc. Power dissipation in modern technologies is an important issue in VLSI. One of the main benefits that reversible logic brings is theoretically zero power dissipation in the sense that, independently of underlying technology and irreversibility means heat generation. In reversible logic gates there is a unique one-to-one mapping between the inputs and outputs. To generate an useful gate function and reversibility of the circuit the reversible gates require some constant inputs and additional unused outputs are required that are referred as the garbage outputs. The proposed reversible multiplier circuit using peres gate and PFAG gate can multiply two 4-bits binary numbers. The proposed reversible 4x4 multiplier circuit can be generalized for NxN bit multiplication. It is used to construct more complex systems in nanotechnology. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterparts.