Open Access Open Access  Restricted Access Subscription or Fee Access

Design of Systolic Based Optimization Tool for FIR Filters Using Binary Tour Method

P. Chandra Shekar, B.S. Prashanth

Abstract


The project is concerned with the design of systolic array by using linear mapping techniques on regular dependence graph (DG), the mapping technique transforms a Dependency graph to a space-time representation, where each node is mapped to a certain processing element and is scheduled to a certain time instance. The systolic design methodology maps an N-dimensional DG to a lower dimensional systolic architecture. The basic vectors involved in the systolic array design should satisfy feasibility condition for designing the tool. MATLAB version 7.01 is the platform used to design the FIR tool for faster implementation, and to achieve low level designs for selected vectors. The tool designed can also be used in selection of Scheduling inequalities and projection vector to meet the feasibility condition, and to achieve 100% HUE using “Tournament Selection” Method. The Tournament selection typically used in Evolutionary Programming, allows for tuning the degree of stringency of the selection imposed, Rather than Selecting on the basis of each Solutions fitness or error in light of the objective function at hand, selection is made on the basis on the number of wins, earned in a competition.

Keywords


Dependence Graph, Processing Element, Systolic Array, Tournament Selection Method.

Full Text:

PDF

References


S.Y. Kung, VLSI Array Processors, Prentice Hall, 1988.

H.T. Kung,”Why systolic architectures?”Computer, vol. 15, p. 37, 1982.

D.I. Moldovan, Parallel Processing: From Applications to Systems. Morgan Kaufmann Publishers.1993.

S.K. Rao. , Regular Iterative Algorithms and their implementation on Processor arrays, Ph.D. Dissertation, Stanford University, Stanford, CA, 1985.

Flynn, M., Some Computer Organizations and Their Effectiveness, IEEE Trans.Comput. Vol. C-21, pp. 948, 1972.

Duncan, Ralph, "A Survey of Parallel Computer Architectures", IEEE, Feb.1990.

De Jong K.A., 1994, Genetic algorithms: A 25-years perspective, in Computational Intelligence: Imitating Life IEEE 1994.

Fogel.L.J. 1994, IEEE, Evolutionary programming in perspective: the top-down view, in: computational Intelligence (pp.135-146).

”A Comparison of methods for self-adaptation in evolutionary algorithms”, N.Saravanan, David E.Fogel, Kevin M.Nelson, IEEE 1995.

M.J Foster and H.T.Kung.”The design of special-purpose VLSI chips,”computer.pp 26-40, Jan 1980, IEEE.

Chapter 7. (pp 189-210), by Keshab K Pharhi.

”Evolutionary Computation 1&2”, by fogel, 1980.

P. Quinton,” The systematic design of systolic arrays,” IRISA Rept., March, 1983.

Sedukhin S.G. and Sedukhin I.S. An interactive graphic CAD tool for the synthesis and analysis of VLSI systolic structures.Proc. of Int. Conf. "Parallel Computing Technologies", 1993, Obninsk, Russia, 1993, Vol.1, pp.163-175.

Jonathan Break, “Systolic Arrays & Their Applications”.

H.T. Kung and C.E. Leiserson, Systolic arrays (for VLSI), Sparse Matrix Proc. 1978, Society for Industrial and Applied Mathematics, 1979, pp. 256-282.

G.J. Li and B.W. Wah, The design of optimal systolic army, Tram. Compute. C-34(10) (1985) 66-75.


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.