

Coverage Implementation for FPGAs used in Tester
Abstract
This Tester Board will incorporate the functionality of Tester Instrument and will be used for testing digital baseband processors, consumer SOCs, and AC Devices. Basically tester tests the ICs by giving different inputs and verify it. It has FPGA. This Paper discusses Verification Techniques through coverage and assertion Implementation. The aim of doing is to cover and verify all the functionalities of tester FPGA Chip. (Here Tester is some client’s project name. I can’t disclose it here. It is generic name). Ultimately we are verifying Tester FPGA Chip by implementing Coverage and assertion by using new techniques.
Keywords
References
Clifford E. Cummings,”System Verilog Assertions Design Tricks and SVA Bind Files”, SNUG 2009
Ms.Anuradha S. Kherde, Prof .P.R. Gumble “International Journal of Advanced Research in Computer Science and Software Engineering”, April 2013
K. Aditya, M. Sivakumar, Fazal Noorbasha, T. Praveen Blessington,“Design and Functional Verification of a SPI Master Slave Core using System Verilog”, June 2016
John Aynsley,“Easier UVM for Functional Verification by Mainstream Users Updated and Extended for UVM 1.0”
Fareha Naqvi, “Design and Implementation of Serial Peripheral Interface Protocol Using Verilog HDL”
K. V. ASHOK KUMAR, M. SANTOSH KRISHNA, “Design and Functional Verification of A SPI Master Slave Core using UVM”
Roopesh D,Siddesha K, Kavitha Narayan B M“RTL DESIGN AND VERIFICATION OF SPI MASTER-SLAVE USING UVM”
Ananthula Srinivas, M.Kiran Kumar, Jugal Kishore Bhandari, “Design and Verification of Serial Peripheral Interface”
Mark Litterick“Using SystemVerilog Assertions for Functional Coverage”, 2005
Robert Wille, Marc Messing, Gorshwin Fey, Gerhard Angst, Lother Linhard, Rolf Drechsler, “Identifying a Subset of SystemVerilog Assertions for Efficient Bounded Model Checking”
Peter Jensen“SVA4T: SystemVerilog Assertions -Techniques, Tips, Tricks, and Traps”, Boston 2004
Roman Wang, Yu Peng, Tang Jin,“Best practices of simplifying code coverage unreachability analysis with IEV in OVM/UVM metric-driven verification”
Accellera Organization, “Universal Verification Methodology (UVM) 1.1 Class Reference”, June 2011
Parth Parmar, “Use VUnits for assertions & functional coverage”, June 2016
Ayas Swain, Kamalakanta Mahapatra“Design and verification of WISHBONE bus interface for System-on-Chip integration”, January 2011
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