Open Access Open Access  Restricted Access Subscription or Fee Access

Performance Analysis of Parallel Prefix Adder Architectures Using Synopsys Tools

M. Ponni, Dr. Karthikeyan Ramamurthi, Dr.P.R. Vaya

Abstract


Binary addition is the most frequently used and speed limiting operation in the design of data path subsystems. There are several ways to formulate addition operation. Different ways provide different implementations. Among them, parallel prefix adder architectures are very much attractive because of their ease in formulation and implementation efficiency. In this paper, we are presenting the performance evaluation and comparison of 16-bit parallel prefix adder architectures namely Ladner-Fischer, Sklansky, Kogge-Stone, Brent-Kung and Han-Carlson. The comparison is done on the basis of three performance parameters i.e. area, power and delay. Out of these adders mentioned above, Han-Carlson architecture is found to be the best compromise.

Keywords


Parallel Prefix Adder, Synopsys.

Full Text:

PDF

References


Neil H. E. Weste, David Harris, Ayan Banerjee, “CMOS VLSI Design”, Pearson Education, 3rd Edition, 2009.

J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, A Design Perspective, Prentice Hall, Upper Saddle River,NJ, 2003.

I. Koren, Computer Arithmetic Algorithms, A.K Peter, Ltd., Natick,MA, 2002.

R.E. Ladner and M.J. Fisher, “Parallel Prefix Computation,” J. ACM, vol. 27, no. 4, pp. 831-838, Oct. 1980.

J. Sklansky, “Conditional-Sum Addition Logic, ” IRE. Transactions on Electronic Computers, vol. EC-9, pp. 226-231, 1960.

P.M. Kogge and H.S. Stone, “A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations,” IEEE Trans. Computers, vol. 22, no. 8, pp. 786-792, Aug. 1973.

R.P. Brent and H.T. Kung, “A Regular Layout for Parallel Adders,” IEEE Trans. Computers, vol. 31, no. 3, pp. 260-264, Mar. 1982.

T. Han and D. Carlson, “Fast Area-Efficient VLSI Adders,” Proc. Symp. Computer Arithmetic, pp. 49-56, May 1987.

R. Zimmermann, “Binary Adder Architectures for Cell-Based VLSI and Their Synthesis,” PhD thesis, Swiss Federal Inst. Of Technology, Zurich, 1997.


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.