Design of Area Efficient Modified Carry Select Adder

Abstract

Carry select adder is mainly used in data processing processor to perform the fast arithmetic operations. The carry select adder divides the words to be added into blocks and forms two sums for each block in parallel, one with assumed carry in Cin of 0 and the other with Cin of 1. The basic carry select adder is not area efficient because it uses multiple pairs of Ripple Carry Adders. Ripple carry adder consists of number of full adder circuits, so it will occupy more area. Each full adder inputs a carry-in, which is the carry-out of the preceding adder. In this paper a modified carry select adder is designed for area efficient. This work uses the Binary to Excess -1 converter and Basic unit instead of Ripple carry adder with Cin=1 in regular carry select adder to achieve lower area. This is achieved by lesser number of logic gates than the n bit full adder in Ripple Carry Adder. The reduced number of gates of this work offers the great advantage in the reduction of area. The design proposed in this paper has been developed using modelsim. In the proposed design, linear carry select adder with binary to excess 1 converter occupies 35 LUT’s. The results analysis shows that the proposed carry select adder structure is better than the conventional carry select adder but it will increases the delay.