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Analysis of Parameters of 8 Bit Multiplies on Behalf of Power Consumption and Delay

Harpreet Singh, Preetinder Singh, Candy Goyal

Abstract


Adders and Multipliers are key components of many high performance systems such as finite impulse response (FIR) filters, microprocessors, digital signal processors, etc. Digital multiplication is one of the most basic functions in a wide range of algorithm. Being the slowest element in the system, the performance of the system is determined by the performance of the multiplier block. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. However, the primary consideration in multipliers has been and continues to be delay as well as power consumption. Power consumption of the multiplier circuit is a very important issue as this power will add up to the total power consumption of the circuit. Depending upon the application there are different types of multipliers are available. Digital multiplier is fast, reliable and efficient components that are utilized to implement any operation. The multiplier is the prime requirement for now days, by implementation of various components and techniques we can improve the performance of the system. In this paper we optimize the parameters of three different techniques e.g. conventional static CMOS logic, Complimentary pass transistor logic, double pass transistor logic. The parameters are evaluated through TARNER 13 software which is the implementation of Very large Scale Integration for the techniques as discussed in the section.

Keywords


CMOS, CPTL, CSL, DPL, RC (Resistance Capacitor), VLSI.

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References


A. P. Chandrakasan, S. Sheng and R. W. Brodersen,“Low-Power CMOS Digital Design”, IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473-484, 1992.

A. P. Chandrakasan and W. Brodersen, “Minimizing Power Consumption in Digital CMOS Circuits”, Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, 1995.

A. Fish and I. Shwartz, “Gate Diffusion Input (GDI) Logic Standard CMOS Nanoscale Process”, 26th convention of IEEE in Israel, pp. 776-780, 2010.

D. Radhakrishnan, “Low Voltage Low Power CMOS Full Adder”, IEE Proceedings, Circuits Devices Systems, vol. 148, no. 1, pp. 19-24, 2001.

D. Wang, M. Yang, W. Cheng, X. Guan, Z. Zhu and Y. Yang, “Novel Low Power Full Adder Cells in 180nm CMOS Technology”, Industrial Electronics and Applications, 2009, ICIEA 2009, 4th IEEE Conference on Digital Object Identifier, pp. 430-433, 2009.

I. A. Wagner, A. Morgenshteid and A. Fish, “Gate-Diffusion Input (GDI) - a novel power efficient method for digital circuits: a design methodology”, ASIC/SOC conference proceedings, 14th Annual IEEE International, pp. 39-43, 2001.

I. S. Abu-Khater, A. Bellaouar and M. I. Elmastry, “Circuits Techniques for CMOS Low-Power High Performance Multipliers”, IEEE Journal of Solid-State Circuits, vol. 31, no.10, pp. 1535-1546, 1996.

K. Roy, S. Mukhopadhyay and H. Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits”, Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, 2003.

P. C. H. Meier, “Analysis and Design of Low Power Digital Multipliers, “PhD Thesis Carnegie Mellon University, Department of Electrical and Computer Engineering, Pittsburgh, Pennsylvania, 1999.

M. Alioto and G. Palumbo, “Analysis and Comparison on Full Adder Block in Submicron Technology”, IEEE transactions on very large scale integration (VLSI) systems, vol. 10, no. 6, pp. 806-823, 2002.

Navdeep Goel,Lalit Garg, “Comparative Analysis of 4-bit CMOS Multipliers” International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011.

P. M. Lee, C. H. Hsu and Y. H. Hung, “Novel 10-T full adders realized by GDI structure”, IEEE international symposium on integrated circuits, pp. 115-118, 2007.

P. G. Parate, P. S. Patil, S. Subbaraman, “ASIC Implementation of 4 Bit Multipliers”, First International Conference on Emerging Trends in Engineering and Technology, IEEE, pp. 408-413, 2009.

R. Zimmermann and W. Fichtner, “Low-Power Logic Styles: CMOS versus Pass-Transistor Logic”, IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, 1997.

S. Mukhopadhyay, C. Neau, R. Tamer, A. Agarwal, C. H. Kim and K. Roy, ”Gate Leakage Reduction for Scaled Devices Using Transistor Stacking”, IEEE transactions on very large scale integration (VLSI) systems, vol. 11, no. 4, pp. 716-730, 2003.


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