Genetic Algorithm to Optimize Test Cases for Simple Digital Circuits

Abstract

Time is Gold! This is a phrase that is being put to use by almost everyone today. Lesser the time spent in doing something, more is the money saved. That thought is at the back of every test engineer’s mind. With the advances in science and technology, modern devices are becoming more and more complex every day. As the device complexity increases, testing becomes even more complex. Circuits are shrinking in physical size while growing both in speed and range of capabilities. This rapid advancement is not without serious problems, however. Especially worrisome are verification and testing, which become more important as the system complexity increases and time-to-market decreases. This results in increased test time and higher test cost. At the same time, the manufacturing cost of a device is reduced due to the higher levels of integration. All this has contributed to a test cost that is an increasing fraction of the total manufacturing cost. Hence the necessity of reducing the test cost. To decrease the test cost, the time required to test a device needs to be decreased. So, we simply need to devise a test set that is small in size.

Many of the optimization problems in circuit design, layout, and test automation can be solved with high-quality results using genetic algorithms.  Genetic algorithms have been very effective for circuits test generation, especially when combined with deterministic algorithm.  In this paper, a new genetic approach to minimize test patterns for simple combinational circuits is presented. In the proposed work evolutionary principles are employed in test minimization stage alone.  Results show that test sets generated using the new approach are more compact for many circuits