Energy Consumption Optimization for Basic Arithmetic Circuits with Transistor Sizing Based on Modified Genetic Algorithm

Abstract

One of the significant factors for evaluating the circuit performance is transistor sizing. Thus for offering better evaluation, an optimal size of transistor is required. The purpose of the optimization is to reduce the power-delay product or the energy requirement by the circuit. The power and delay are mainly based on the size of transistor. There are many technique exists for optimizing the size of transistor for reducing the power consumption. But all these techniques resulted in poor performance for larger transistors. To overcome those demerits, genetic algorithm is used. Genetic algorithm has the capacity of minimizing the search problem complexity uses the transistor sizing which is usually a type of search problem in the large multidimensional search space for energy reduction. This technique shows better performance when compared to the Hybrid Tree Structure technique. For further improving the performance, a modified genetic algorithm is proposed in this paper for determining the transistor size which in turn leads to better reduction of power consumption.