Design and Performance Analysis of Various Multipliers using Verilog HDL

Maroju SaiKumar; P. Samundiswary

Design and Performance Analysis of Various Multipliers using Verilog HDL

Maroju SaiKumar, P. Samundiswary

Abstract

In the domain of VLSI design, the multipliers have play an vital role. Multipliers are the basic building blocks of digital design. Multipliers are used in Digital Signal Processing applications (DSP) such as Fast Fourier Transform (FFT), Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters. In this paper, the design of various multipliers such as Array Multiplier (AM), Modified Radix-2 booth multiplier (MRBM), Ripple Carry Multiplier (RCM) with Row bypassing, Wallace Tree Multiplier (WT), Dadda Multiplier (DM) and Vedic Multiplier (VM) are discussed and their performance parameters such as area and delay are determined and compared. The various multipliers are designed using Verilog HDL. Then, they are simulated and synthesized using Xilinx ISE 13.2 for Virtex-6 family device with a speed grade of -2.

Keywords

Array Multiplier (AM), Modified Radix-2 Booth Multiplier (MRBM), Ripple Carry Multiplier with Row Bypassing (RCM), Wallace Tree Multiplier (WT), Dadda Multiplier (DM) and Vedic Multiplier (VM), FPGA, Xilinx ISE.

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References

Chris Y.H. Lee, Lo Hai Hiung, Sean W.F. Lee, Nor Hisham Hamid, “A Performance Comparison Study on Multiplier Designs”, Proceedings of IEEE International Conference on Intelligent and Advanced Systems, Malaysia, pp.1-6, June 2010.

Swee K.L.S, Lo Hai Hiung, “Performance Comparison Review of 32-bit Multiplier Designs”, Proceedings of IEEE International Conference on Intelligent and Advance Systems, Kuala Lumpur, Malaysia, vol.2, pp.836-841, June 2012.

K.M K.M.Prabhakaran, A.Karthika, “Low Complexity and High Accuracy Fixed Width Modified Booth Multiplier”, International Journal of Scientific and Research Publications, vol.3, no.3, pp.1-4, Mar 2013.

Prathibadevi Tapashetti, A.S. Umesh, Ashalatha Kulshrestha, “Design and Simulation of Energy Efficient Full Adder for Systolic Array”, International Journal of Soft Computing and Engineering, vol.1, no.6, pp.356-360, Jan 2012.

Kripa Mathew, S.Asha Latha, T.Ravi, E.Logashanmugam, “Design and Analysis of Array Multiplier using an Area Efficient Full Adder Cell in 32nm CMOS Technology”, International Journal of Engineering and Science, vol.2, no.3, pp.8-16, Mar 2013123–135.

Young-Ho Seo, Dong-Wook Kim, “A New VLSI Architecture of Parallel Multiplier-Accumulate Based on Radix-2 Modified Booth Alogirithm”, IEEE Transactions on VLSI Systems, vol.18, no.2, pp.201-207, Feb 2010.

Raminder Preet Pal Singh, Praveen Kumar, and Balwinder Singh, “Performance Analysis of 32-bit Array Multiplier with a Carry Save Adder and with a Carry Look Ahead Adder”, Letters of International Journal of Recent Trends in Engineering, vol.2, no.6, pp. 83-89, Nov 2009.

Ko-Chi Kuo , Chi-Wen Chou, “Low Power and High Speed Multiplier Design with Row Bypassing and Parallel Architecture”, Elsevier Journal of Microelectronics, no.41, pp.639-650, July 2010.

Maroju SaiKumar, Dr. P.Samundiswary, “Design and Performance Analysis of Various Adders using Verilog”, International Journal of Computer Science and Mobile Computing, vol.2, issue.9, pp.128-138, Sep 2013.

Ron S. Waters and Earl E. Swartzlander, Jr., "A Reduced Complexity Wallace Multiplier Reduction,” IEEE Transactions On Computers, vol. 59, no. 8, pp.1134-1137, Aug 2010.

Jasbir Kaur, Kavita, “Structural VHDL Implementation of Wallace Multiplier”, International Journal of Scientific & Engineering Research, vol.4, issue.4, pp.1829-1833, Apr 2013.

Anju S, M Saravana, “High Performance Dadda Multiplier Implementation using High Speed Carry Select Adder”, International Journal of Advance Research in Computer and Communication Engineering, vol.2, issue.3, March 2013.

Poornima M, Shivaraj Kumar Patil, Shivukumar, Sridhar K P, Sanjay H, “Implementation of Multiplier using Vedic Algorithm”, International Journal of and Exploring Engineering , vol.2, issue.6, pp.219-223, May 2013.

R.Uma, Vidya Vijayan, M.Mohanapriya, Sharon Paul, “Area, Delay and Power Comparison of Adder Topologies”, International Journal of VLSI Design and Communication Systems, vol.3, no.1, Feb 2012.

Xilinx13.4, “Synthesis and Simulation Design Guide”, UG626 (v13.4) January 19, 2012.

Xilinx 13.1, “RTL and Technology Schematic Viewers Tutorial”, UG685 (v13.1), March 1, 2011.

Xilinx, “7 Series FPGAs Configurable Logic Block”, UG 474 (v 1.5), August 6, 2013.

Xilinx 12.4, “ISim User Guide”, UG660 (v 12.4), December 14, 2010.

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