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Design of ECC Co-Processor Architecture and Estimation of Resource Binding with Increased Key Size
Abstract
The security level of Elliptic Curve Cryptography (ECC) system depends on the hardness of finding the discrete logarithm in a finite field, the curve parameters selection, bit length etc. Increased demand of security level insists the cryptosystem to prepare for higher key size. When the computational intensive ECC algorithm is implemented on field programmable gate arrays (FPGAs), the resource consumption is one of the key issues. The first objective of this paper is paving the steps in the design of typical ECC processor using ModelSim 5.7 and Xilinx 9.2i, and evaluating the performance measures viz. the hardware efficiency, the functionality efficiency, the area and power calculations. Secondly, this work implements an unique co-processor architecture for two different key sizes (160-bit and 256-bit) to figure out the absolute resource usage differences in term of power, area and speed. The bit length is the major parameter in key generation processes that deals with the time consuming operation scalar multiplication. ECC architectures over GF(2256) is designed with an efficient array multiplier and Montgomery scalar multiplication algorithm. The simulation result shows that with frequency 100MHz, the power consumption of ECC co-processor is 824mW and its occupies 27114 LUT’s and 1,64,292 gates. The architectures are implemented in Spartan3E family device XC3S1600E.
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