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Pseudo-Exhaustive Pattern Generators for BIST

N. Vijay, N. Muthumohanraj, A. Sathish Kumar


Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation. In (n,k)-adjacent bit pseudo-exhaustive test sets, all 2^k binary combinations appear to all adjacent k-bit groups of inputs. With recursive pseudo-exhaustive generation, more than one module can be pseudo-exhaustively tested in parallel. In order to detect sequential (e.g., stuck-open) faults that occur into current CMOS circuits, two-pattern tests are exercised. Also, delay testing, commonly used to assure correct circuit operation at clock speed requires two-pattern tests. In this paper a pseudo-exhaustive two-pattern generator is presented, that recursively generates all two-pattern (n,k)-adjacent bit pseudo-exhaustive tests for all . To the best of our knowledge, this is the first time in the open literature that the subject of recursive pseudo-exhaustive two-pattern testing is being dealt with. A software-based implementation with no hardware overhead is also presented.


Built-In Self-Test (BIST), Pseudoexchaustive Two pattern Testing, Test Pattern Generation

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