### Design of a CMOS Parallel Counter with Improved Operating Frequency

#### Abstract

Counters are one among the basic building block in

every digital system. It is an essential building block for a variety of circuit operations such as programmable frequency dividers, shifters, code generators and various arithmetic operations. Since these fundamental operations comprises of many applications main focus is for an efficient counter design. In this paper a new parallel counter is designed that achieve high operating frequency. The high operating

frequency is achieved by pipeline partitioning methodology which consists of a counting path and a state look ahead. The counting path’s counting logic controls counting operations and it consist of 2- bit counting modules. State look ahead path’s state look ahead logic anticipates the future states and thus prepares the counting path for these future states. In this counter architecture there are three simple

repeated CMOS logic modules types: an initial module generates anticipated counting states for higher significant bit modules through state look-ahead path, simple D-type flip-flops and 2-bit counters. The state look-ahead path prepares the counting paths next counter state with respect to clock. The clock edge triggers all modules

simultaneously thus concurrently updating the current state with a uniform delay with all counting modules. Here, as an example a 8-bit counter is designed with the pipeline partitioning methodology and is simulated by DSCH & Microwind tool. The structure is scalable to

arbitrary N-bit counters using the three module types.

#### Keywords

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PDF#### References

Saleh Abdel-Hafeez and Ann Gordan-Ross, “A digital CMOS parallel

counter architecture based on state look ahead logic,” IEEE Trans. VLSI

systems, vol.19, no.6, June 2011

Ercegovac M. and Lang T.( Jun 1989), “Binary counters with counting

period of one half adder independent of Counter size,” IEEE Trans.

Circuits Syst.

Vuillemin J. E.,(1991)“Constant time arbitrary length synchronous

binary counters,” in Proc. IEEE 10th Symp. Comput. Arith., , pp.180–

Hoppe B., Kroh C., Meuth H., and Stohr M., (Sep. 1998)“A 440MHz16

bit counter in CMOS standard cells,” in Proc. IEEE Int. ASIC Conf., ,

vol. 244.

Alioto M., Mita R., and Palumbo G.(Nov. 2006), “Design of high-speed

power-efficient MOS current-mode logic frequency dividers,” IEEE

Trans. Circuits Syst. II, Expr. Briefs, vol. 53, no. 11, pp. 1165–1169.

Stan M. R., Tenca A. F., and Ercegovac M. D.(Jul. 1998), “Long and

fast up/down counters,” IEEE Trans. Comput., vol. 47, no. 7, pp. 722–

Stan M. R(Jul. 1997)., “Synchronous up/down counter with period

independent of counter size,” in Proc. IEEE Symp. Comput. Arith.,

Asilomar, CA, , pp. 274–281.

Stan M. R.(2004), “Systolic counters with unique zero state,” in Proc.

IEEE Proc. Int. Symp. Circuits Syst. (ISCAS), , pp. II-909–II-912.

Pekmestzi K. Z. and Thanasouras N. (Nov. 1994), “Systolic frequencydividers

counters,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal

Process., vol. 41, no. 11, pp. 775–776.

Lutz D. R. and Jayasimha (Nov. 1996), “Programmable modulo-K

counters,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 43,

no. 11, pp. 939–941.

C. Yeh, B. Parhami, and Y. Wang, “Designs of counters with near

minimal counting/sampling period and hardware complexity,” in Proc.

Asilomar Conf. Signals, Syst., Comput., 2000, pp. 894–898.

Y. Leblebici, H. Ozdemir, A. Kepkep, and U. Cilingiroglu, “A compact

high-speed (31, 5) parallel counter circuit based on capacitive thresholdlogic

gates,” IEEE J. Solid-State Circuits, vol. 31, no. 8, pp. 1177–1183,

Aug. 1996.

P. Lin, K. E. Kerr, and A. S. Botha, “A novel approach for CMOS

parallel counter design,” in Proc. 25th EUROMICRO Conf., 1999,

pp.112–119.

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