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Modified Logic Parallel Pipelined Architecture for Enhanced Throughput of Advanced Encryption

V.A. Suryawanshi, G. C. Manna, Dr.S.S. Dorale


There is an increasing demand for computer networks from individuals and organization for professional activities. Current secure applications often need encrypted channels with high throughput, of the order of gigabits per second. This paper presents a efficient hardware design increasing throughput for the Advance Encryption Standard (AES) algorithm, using a high-speed pipelined architecture. In this hardware architecture, initially generated keys are stored immediately in a memory block and encryption process implemented in parallel. It reduces the required hardware resources and achieves high-speed performance. In low covered area resources this design performs better. Compared to other pipeline based implementations, its throughput can reach 20.832 Gbit/sec, which is the highest in non-ASIC, non inner round class of pipeline hardware architecture.


AES, FPGA, Pipelined Key Design and VHDL.

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National Institute of Standards and Technology (NIST), Advanced Encryption Standard (AES) Federal Information Processing Standards Publication 197 (FIPS PUB 197), Nov. 2001.

X. Zhang and K. K. Parhi,, “High-Speed VLSI Architectures for the AES Algorithm”, IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 12, no. 9, September 2004.

Deen Kotturi, Seong-Moo Yoo, Blizzard, J.; “AES Crypto Chip Utilizing High-Speed Parallel Pipelined Architecture”, IEEE International Symposium on Circuits and Systems,ISCAS2005.23- 26 May 2005 Page(s):4653 – 4656 Vol. 5

Tanzilur Rahman, Shengyi Pan, Qi Zhang “Design of a High Throughput 128-bit AES” Procedings of the International Multi Conference of Engineers and Computer Scientists 2010 VOL II IMECS 2010 Hong Kong.

Nadia Nedjah, Luiza de Macedo Mourelle , Marco Paulo Cardoso “A Compact Piplined Hardware Implementation of the AES-128 Cipher” Proceedings of the Third International Conference on Information Technology: New Generations (ITNG’06) 0-7695-2497-4/06 $20.00 © 2006 IEEE

Alireza Hodjat, Student Member, IEEE, and Ingrid Verbauwhede,Senior Member, IEEE “Area-Throughput Trade- Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors” IEEE TRANSACTIONS ON COMPUTERS, VOL. 55, NO.4, APRIL 2006

Paolo Maistri, Régis Leveugle “10-gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard” 2011 14th Euromicro Conference on Digital System Design

Howard M. Heys, Member, IEEE, and Liang Zhang “Pipelined Statistical Cipher Feedback:A New Mode for High-Speed Self- Synchronizing Stream Encryption” IEEE TRANSACTIONS ON COMPUTERS, VOL. 60, NO. 11, NOVEMBER 2`011

H. Li “Efficient and flexible architecture for AES” The Institution of Engineering and Technology IEE Proc.-Circuits Devices Syst.Vol. 153, No. 6, December 2006

Chih-Peng Fan and Jun-Kui Hwang “Implementations of High Throughput Sequential and Fully Pipelined AES Processors on FPGA” Proceedings of 2007 International Symposium on Intelligent Signal Processing and Communication Systems Nov.28-Dec.1, 2007 Xiamen, China

Hua Li and Jianzhou Li “A New Compact Architecture for AES with Optimized ShiftRows Operation” 1-4244-0921-7/07 2007 IEEE

Solmaz Ghaznavi, Catherine Gebotys,and Reouven Elbaz “Efficient Technique for the FPGA Implementation of the AES Mix Columns Transformation” 2009 International Conference on Reconfigurable Computing and FPGAs 2009 IEEE

N. Sklavos and O. Koufopavlou, “Architectures and VLSI Implementations of the AES-Proposal Rijndael” IEEE TRANSACTIONS ON COMPUTERS, VOL. 51, NO.12, DECEMBER 2002.



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