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An Energy Efficient Layered Decoding Architecture for LDPC Decoder

A.N. Jayanthi, Dr C S Ravichandran


Low-density parity-check (LDPC) decoder requires large amount of memory access which leads to high energy consumption. To reduce the energy consumption of the LDPC decoder, memory-bypassing scheme has been proposed for the layered decoding architecture which reduces the amount of access to the memory storing the soft posterior reliability values. In this work, a scheme that achieves the optimal reduction of memory access for the memory bypassing scheme is presented. The amount of achievable memory bypassing depends on the decoding order of the layers. In this proposal the problem of finding the optimal decoding order and propose algorithm to obtain the optimal solution and also the corresponding architecture which combines some of memory components and results in reduction of memory area.


Low Power, Low-density Parity-check Code, Simulated Annealing

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R. G. Gallager, “Low-density parity-check codes,” IRE Trans. Inf.Theory, vol. IT-8, pp. 21–28, Jan. 1962.

D. J. C. MacKay, “Good error-correcting codes based on very sparsematrices,” IEEE Trans. Inf. Theory, vol. 45, no. 2, pp. 399–431, Mar. 1999.

Digital Video Broadcasting (DVB); Second Generation Framing Structure, Channel Coding and Modulation Systems for Broadcasting, Interactive Services, News Gathering and Other Broadband Satellite Applications 2004.

LDPC coding for OFDMA PHY. 802.16REVe Sponsor Ballot Recirculation Comment 2004, IEEE C802.16e-04/141r2.

Joint Proposal: High Throughput Extension to the 802.11 Standard: PHY. IEEE P802.11 Wireless LANs 2006, IEEE 802.11-05/1102r4.

R. Tanner, “A recursive approach to low complexity codes,” IEEE Trans. Inf. Theory, vol. 27, no. 5, pp. 533–547, Sep. 1981.

A. J. Blanksby and C. J. Howland, “A 690-mW 1 Gb/s 1024-b, rate ½ low-density parity-check code decoder,” IEEE J. Solid-State Circuits, vol. 37, pp. 404–412, Mar. 2002.

J. Zhang and M. P. C. Fossorier, “Shuffled iterative decoding,” IEEE Trans. Commun., vol. 53, no. 2, pp. 209–213, Feb. 2005.

M. M. Mansour and N. R. Shanbhag, “High throughput LDPC decoders,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 6, pp. 976–996, Dec. 2003.

E. Cavus, “Techniques for the decoding of low density parity check codes: efficient simulation, algorithm improvement and implementation,” Ph.D dissertation, UCLA, Los Angeles, 2007.


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