An Energy Efficient Layered Decoding Architecture for LDPC Decoder

Abstract

Low-density parity-check (LDPC) decoder requires large amount of memory access which leads to high energy consumption. To reduce the energy consumption of the LDPC decoder, memory-bypassing scheme has been proposed for the layered decoding architecture which reduces the amount of access to the memory storing the soft posterior reliability values. In this work, a scheme that achieves the optimal reduction of memory access for the memory bypassing scheme is presented. The amount of achievable memory bypassing depends on the decoding order of the layers. In this proposal the problem of finding the optimal decoding order and propose algorithm to obtain the optimal solution and also the corresponding architecture which combines some of memory components and results in reduction of memory area.