Open Access Open Access  Restricted Access Subscription or Fee Access

An Inspired Error Correction Codes for Multiple-Cell Upsets and Its Applications

S. Midhuna Chandran, K. Nandhini, M. Nazrin Banu, P. Pavithra

Abstract


The faults suffered by SRAM cell have grown due to the continuous technology scaling. The possibility of occurrence of single-cell variation and multiple-cell variation are also increasing. The random and burst MCUs in space and other wireless applications occur due to cosmic waves. The proposed system provides a dual-mode error correction mechanism for detecting and rectifying multi cell error which is adjacent and also random. A good trade-off is achieved between error recovery and redundancy reduction for 2, 3, and 4-bit burst errors compared to existing methods. Their parity generation and syndrome mechanism is also efficient in terms of area, power, and delay. To detect and correct random errors a direct and cross vertical parity generation is employed, which results in efficient error correction for most of the random error cases. A series of code combination for adjacent and random error results in efficient redundancy and error correction compared with other existing mechanisms.


Keywords


Error Correction Codes (ECCs), Fault Tolerance, Multiple-Cell Variation (MCV), Stability.

Full Text:

PDF

References


The International Technology Roadmap for Semiconductors. (2013). [Online]. Available: http://www.itrs2.net/2013-itrs.html

S. K. Kurinec and K. Iniewski, Nanoscale Semiconductor Memories: Technology and Application. Boca Raton, FL, USA: CRC Press, 2014.

J. Barak, M. Murat, and A. Akkerman, “SEU due to electrons in silicon devices with nanometric sensitive volumes and small critical charge,” Nucl. Instrum. Methods Phys. Res. B, Beam Interact. Mater. At., vol. 287, pp. 113–119, Sep. 2012.

E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba, “Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule,” IEEE Trans. Electron Devices, vol. 57, no. 7, pp. 1527–1538, Jul. 2010.

G. Tsiligiannis et al., “Multiple cell upset classification in commercial SRAMs,” IEEE Trans. Nucl. Sci., vol. 61, no. 4, pp. 1747–1754, Aug. 2014.

G. I. Zebrev, K. S. Zemtsov, R. G. Useinov, M. S. Gorbunov, V. V. Emeliyanov, and A. I. Ozerov, “Multiple cell upset cross-section uncertainty in nanoscale memories: Microdosimetric approach,” in Proc. 15th Eur. Conf. Radiat. Effects Compon. Syst. (RADECS), Sep. 2015, pp. 1–5.

N. Chechenin and M. Sajid, “Multiple cell upsets rate estimation for 65 nm SRAM bit-cell in space radiation environment,” in Proc. 3rd Int. Conf. Exhib. Satell. Space Missions, May 2017, p. 77.

N. N. Mahatme, B. L. Bhuva, Y.-P. Fang, and A. S. Oates, “Impact of strained-Si PMOS transistors on SRAM soft error rates,” IEEE Trans. Nucl. Sci., vol. 59, no. 4, pp. 845–850, Aug. 2012.

Y. Bentoutou, “Program memories error detection and correction onboard earth observation satellites,” Int. J. Elect. Comput. Eng., vol. 4, no. 6, pp. 933–936, 2010.

L. J. Saiz-Adalid et al., “Flexible unequal error control codes with selectable error detection and correction levels,” in Proc. 32th Int. Conf. Comput. Safety, Rel. Secur. (SAFECOMP), Sep. 2013, pp. 178–189.

Jing Guo, Liyi Xiao, Zhigang Mao, and Qiang Zhao., “Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code,” IEEE Trans. Nucl. IEEE Trans.on VLSI, vol. 22, no. 2, pp. 1747–1754, Jan. 2014.


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.