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A Low Power VLSI ASIC 3-Dimensinal Discrete Wavelet Transform Architecture for Video Coding using Lifting Scheme

Ganapathi Hegde, Pukhraj Vaya

Abstract


This paper presents an efficient high speed, low power 3-Dimensinal Discrete wavelet transform (3-D DWT) architecture for video coding applications. 3-D DWT architecture is designed for 8*8*8 video frame, based on fast lifting scheme approach using (5/3) wavelet filter. It reduces the hardware complexity, memory accesses and achieves good quality of reconstruction for images. Sub blocks of the architecture are modeled in Verilog Hardware description language (Verilog HDL). The Application specific integrated circuit (ASIC) implementation results of 3-D DWT show that the proposed architecture achieves 29% improvement in power and operates at a maximum frequency of 380MHz. It can be used as a full custom design for video processing application.

Keywords


3-D DWT, Lifting Scheme, ASIC, Video Processing

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References


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