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Double Tail Comparator with Cascode to Parallel Connection for Reducing Delay

S. Madhumathi, J. Ramesh Kumar


A new double tail parallel latch load comparator are compared in term of voltage, power, delay. CMOS dynamic comparator which has dual input, dual output inverter stage suitable for high speed analog-to-digital converters with low voltage and low power. A single tail comparator is replaced with a double tail dynamic comparator which reduces the power and voltage by increasing the speed. The technology scaling of MOS transistors enables low voltage and low power operation which decreases the offset voltage and delay of the comparator .The proposed algorithm replaces some pair of transistors connected in parallel for offset voltage reduction in double tail comparator due to mismatch in transistor pairs. Low voltage and low power consumption are the two most important parameter of the comparator which is to be used in high speed ADCs. 0.25μm CMOS technology confirms the analysis result, frequency=41MHz and given supply voltage will be 0.8v


Double-Tail Comparator, Latch Load, Offset Reduction.

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