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Area and Power Efficient DWT using Reduced Complexity Wallace Multiplier
Abstract
VLSI design approach of a high speed and 1-D
Discrete Wavelet Transform (DWT) using Modified Wallace
Multiplier is proposed. Modified Wallace multiplier uses full adders and half adders for area reduction phase. In Full adders the partial product bits are reduced. Due to this the complexity of the modified Wallace multiplier is reduced. Further a Post truncation method is applied to modified Wallace multiplier for area reduction. In this way, it reduces the area and power compared to previous Wallace multiplier. The proposed truncated modified Wallace multiplier for 8*8 bit is applied to 1-D DWT to reduce the area. Modified Wallace multiplier for 8*8 bit, 9*9 bit and 10*10 bit applied in 1-D DWT, its reduces the area and power. Totally, it provides a very high speed processing as well as high quality.
Keywords
References
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