Bus Matrix Synthesis for the Multi Layer AXI Bus Matrix

Abstract

The design complexity increased in SoC design that the ever increasing amount of logic that can be placed onto a single silicon die is driving the development of highly integrated SoC designs. For reducing this complexity, that high performance and low latency is required in on-chip bus. AMBA AXI protocol is an advanced microprocessor system bus interface and is an enhanced bus protocol of the existing advanced high-performance bus (AHB). In AXI in SoC, the interconnected functional blocks can be choosed based on matching of its addresses without using any priority policies.In this, the arbitration is proposed without using priority policies. Area and time delay will be reduced by using this bus matrix in the applications from that data speed can be increased with frequency.