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Design of Fixed-Width Multiplier using Baugh-Wooley Algorithm

V. Sathya, P. Devasundar


This paper focuses on the design of fixed-width multipliers with Baugh-Wooley algorithm. The fixed width multipliers derived from Baugh-Wooley algorithm produce n-bit output product with n-bit multiplier and n-bit multiplicand. In previous papers the fixed-width signed multipliers are designed by using both half-adders and full-adders. In this paper we have designed the fixed width Baugh-Wooley multiplier by using only an array of full-adders and the final Ripple Carry Adder (RCA). We have implemented the Multiply and Accumulate (MAC) unit using fixed width signed multiplier and fixed width Baugh-Woolley multiplier. The main contribution of the proposed work is to reduce the area and power by designing the fixed-width Baugh-Wooley multiplier. We also present the comparison results of parameters like power, area, gates and delay.


Area, Fixed-Width Multiplier, MAC Unit, Multiplication, Power.

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