An Efficient High Speed and Low Area Digital FIR Filter Design Based on Sectioning of Look up Table in Distributed Arithmetic Algorithm
Abstract
Keywords
Full Text:
PDFReferences
Jiafeng Xie,Jianjun He, Guanzheng Tan, “FPGA Realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures”, journal of Microelectronics ,2010,pp. 365-370.
Antonion, “Digital Filters: Analysis, Design, and Applications”, McGraw-Hill, New York, 1993.
S.Yu,E.E.Swartzlander, “DCT implementation with distributed arithmetic”, IEEE Transactions on Computers Vol.9,2001,pp.985–991.
Valeria Garofalo, “Fixed-width multipliers for the implementation of efficient digital FIR filters”, Journal of Microelectronics vol.39 ,2008 , pp.1491–1498.
LeiZhang,Tadeusz Kwasniewski, “FIR filter optimization using bit-edge equalization in high-speed back plane data transmission” , Journal of Microelectronics, vol 40,2009,pp.1449–1457.
M.A.M.Eshtawie and M.Othman, “On-line DA-LUT architecture for high- Speed high-order digital FIR filters”,in : Proceedings of the IEEE International Conference on Communication Systems(ICCS),Singapore,November.2006,Pp.5
Kim Kyung-Saeng, KwyroLee, “Low-power and area efficient FIR filter implementation suitable for multiple tape”, IEEE Transactions on VLSI Systems , vol11 1),2003).
K.K.Parhi,in: “VLSI Digital Signal Processing Systems : Design and Implementation”, Wiley,NewYork,1999.
Sanjay, AttriB.S., Sohi and Y.C.Chopra, “Efficient design of Application Specific DSP cores using FPGAs”, in : International Conference on ASIC Proceedings, 2001,pp.462-466.
P.K.Meher, “Hardware efficient systolization of DA-based calculation of finite digital convolution of finite digital convolution”, IEEE Transactions on Circuit and Systems II : Express Briefs 53(8),2006,pp.707–711.
J.P.Choi, S.C.Shin and J.G.Chung, “Efficient ROM size reduction for distributedarithmetic”,In:Proceedings of the IEEE International Symposium Circuits Systems(ISCAS),2000,pp.61–64.
P.K.Meher, S.chandrasekaran, A.Amira, “FPGA Realization of FIR filters by efficient and flexible Systolization using distributed arithmetic”,IEEE Transactions on Signal Processing 56(7), 2008, pp. 3009–3017.
Refbacks
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.