Open Access Open Access  Restricted Access Subscription or Fee Access

Comparative Design Analysis of Full Adder Logic Using Microwind

T. Muruga Boopathi, S. Ragu Nandhini, I. Ram Vikas, M. Sri Deepika, S. Karthikeyan


An adder is a digital circuit that performs addition. In many computers and other kinds of processors adders are used in the Arithmetic Logic Units (ALU). They are also utilized in other parts of the processor, where they are used to calculate addresses, increment and decrement operators, and similar operations. The rapid increase in the number of transistors on chips has enabled a dramatic increase in the performance of computing systems. Area optimization is also considered as a major factor in deciding the effectiveness and this can be achieved by reducing the transistor count.

Full Text:



Ranjeeta Verma, Rajesh Mehra, “CMOS Based Design Simulation of Adder /Subtractor Using Different Foundries”, International Journal of Science and Engineering, Vol. 2, Issue 1, pp. 22-27, 2013.

R. Singh, R. Mehra, “Low power TG full adder design using CMOS Nano technology”, 2nd IEEE International Conference on Parallel Distributed and Grid Computing, Vol. 2, pp. 210-213, Dec 2012.

A. Sharma, R. Mehra, “Area and Power efficient CMOS Adder design by hybridising PTL and GDI technique”, International Journal of Computer Applications, Vol. 6, Issue 5, pp. 15-22.

Pradeep Kumar, “Existing Full Adders and Their Comparison on The Basis of Simulation Result And to design a improved LPFA (Low Power Full Adder)”, International Journal of Engineering Research and Applications, Vol. 2, Issue 6, pp. 599-606, Nov-Dec 2012.

Vandana Choudhary, Rajesh Mehra, “2- Bit Comparator Using Different Logic Style of Full Adder”, International Journal of Soft Computing and Engineering (IJSCE), Vol. 3, Issue 2, pp. 277-279, May 2013.

Monikashree T. S, Usharani. S, Dr. J. S. Baligar, “Design and Implementation of Full Subtractor using CMOS 180nm Technology”, International Journal of Science, Engineering and Technology Research (IJSETR), Vol. 3, Issue 5, pp. 1421-1426, May 2014.

Hiroshi Hatano, “Single Event Effects on Static and Clocked Cascade Voltage Switch Logic (CVSL) Circuits”, IEEE Transactions on Nuclear Science, Vol. 56, Issue. 4, pp. 1987-1991, Aug 2009.

Hiroshi Hatano, “SET Immune Space borne CVSL and C2VSL Circuits”, Journal of Electrical and Control Engineering, Vol. 3, Issue 5, pp. 43-48, 2013.

Abutaleb, M. M. "A new static differential design style for hybrid SET–CMOS logic circuits", Journal of Computational Electronics, 2015.

Magdy A. Bayoumi. "Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic- Like Static CMOS Circuit Family", 9th International Symposium on Quality Electronic Design, March 2008.

Priyadarshini. V, “Power-Area trade-off for Different CMOS Design Technologies”, Int. J. Computer Technology & Applications, Vol 3, Issue 4, pp. 1388-1394, July-August 2012.

Dae Woon Kang, Yong Bin Kim, “Design of Enhanced Differential Cascade Voltage Switch Logic (EDCVSL) Circuits for High fan In Gate”, IEEE, pp. 309- 313, 2002.

D. Somasekhar, K. Roy, “differential Current Switch Logic: A low power DCVS logic family”, IEEE J. Solid-State Circuits, Vol. 31, pp. 981-991, July 1996.

Ms. Amrita Pahadi, Dr. Uma Rathore Bhatt, “Layout Design, Analysis and Implementation of Combinational and Sequential Circuits using Microwind”, SSRG International Journal of VLSI & Signal Processing, vol. 2, Issue 4, pp. 6- 14, July-August 2015.


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.