A Novel VLSI Architecture with Reduced Hard Multiple based on Higher Radix Hybrid Modified Booth Algorithm
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“A New VLSI Architecture of Parallel Multiplier– Accumulator Based on Radix-2 Modified Booth Algorithm”,Young-Ho Seo, Member, IEEE, and Dong-Wook Kim, Member, IEEE, IEEE Transactions On Very large Scale Integration (VLSI) Systems, Vol. 18, No. 2, Feb 2010.
Li-Rong Wang, Shyh-Jye Jou and Chung-Len Lee,“A Well-structured modified Booth Multiplier Design” 978-1-4244-1617-2/08/$25.00 © IEEE 2008
Naresh R. Shanbhag and P. Juneja, “parallel implementation of a 4x4-bit multiplier using modified booth‟s algorithm”, IEEE Journal of solid-state circuits, vol.23, No.4, pp. 1010-13, august 1998
Masayuki Ito, David Chinnery, Kurt Keutzer. : „Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition‟ International Conference on Computer Design, pp. 21-26, October, 2003.
Villeger and V.G. Oklobdzija, “Evaluation of Booth Encoding Techniques for Parallel Multiplier Implementation,”Elect. Lett., vol. 29, no. 23, pp. 2,016-2,017, Nov. 1993.
J. Choi, J. Jeon, and K. Choi, “Power minimization of functional units by partially guarded computation,” in Proc. IEEE Int. Symp. LP Electron. Des., 2000, pp. 131–136
O. Chen, R. Sheen, and S. Wang, “A low-power adder operating on effective dynamic data ranges,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 4, pp. 435–453, Aug. 2002
H. Lee, “A power-aware scalable pipelined Booth multiplier,” in Proc. IEEE Int. SOC Conf., 2004, pp. 123–126.
J. Ohban, V. G. Moshnyaga, and K. Inoue, “Multiplier energy reduction through bypassing of partial products,” 2002 Asia - Pacific Conference on Circuits and Systems (APCCAS ‟02), vol. 2, pp. 13-17, Oct. 2002.
M. Roorda, “Method to Reduce the Sign Bit Extension in A Multiplier that Uses the Modified Booth Algorithm”, 1986 electronic lett. vol.22, No.20, pp.1061-62, 12th august 1986.
Naresh R. Shanbhag and P. Juneja, “parallel implementation of a 4x4-bit multiplier using modified booth‟s algorithm”, IEEE Journal of solid-state circuits, vol.23, No.4, pp. 1010-13, august 1988.
V. Poornaiah and P.V. Ananda Mohan, “Design of a 3 –bit Recoded Booth Recoded Novel VLSI Concurrent Multiplier - Accumulator Architecture”, IEEE 8th international conf. on VLSI Design, pp. 392-397, January 1995.
Wen-Chang Yeh and Chein-Wei Jen,“High-Speed Booth Encoded Parallel Multiplier Design “, IEEE Tran. On Computers, vol. 49, No. 7, pp. 692 -701, July 2000.
Li-Rong Wang, Shyh-Jye Jou and Chung-Len Lee,“A Wellstructured modified Booth Multiplier Design” 978-1-4244- 1617-2/08/$25.00 © IEEE 2008.
Rizwan Mudassir , Mohab Anis and Javid Jaffari, “Switching Activity Reduction in Low Power Booth Multiplier” , 978 -1- 4244-1684-4/08/$25.00 © IEEE 2008.
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