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Implementation of Reconfigurable Redundant Radix- 4 Arithmetic Co-processor

M. Naveenkumar, Sunil S. Mathad

Abstract


This paper deals with the design and implementation of a Field Programmable Gate Array (FPGA) based co-processor called Redundant Radix-4 Arithmetic co-processor. In the proposed work different arithmetic operations addition, subtraction, complementation, multiplication, square, division left shift and right shift are implemented. These arithmetic operations are implemented using Redundant Radix-4 (RR-4) number system for achieving high speed. The binary numbers are converted to RR-4 and these numbers are used for arithmetic operations. This RR-4 number system will carry out the operations in parallel. Parallel addition of two m-digit redundant binary numbers can be performed in a same interval of time independent of m, without using propagated carry. The proposed co-processor is developed by set of Very High Speed Integrated Circuit Hardware Description Language (VHDL) modules for fast parallel arithmetic operations. The implementation is done through different stages of Xilinx Integrated Software Environment (ISE) 12.4 and physical verification is carried out on Virtex 5 XC5VLX110T Field Programmable Gate Array (FPGA). The simulation results of co-processor are observed using Xilinx ISim simulator. The co-processor is interfaced with the Chipscope Pro Virtual Input-Output (VIO) console, to enter data from the keyboard and to get back the result in VIO console window. This co-processor occupies area of 2281.52 μm2 and 407.848 MB of memory with switching power 1.02489371 mW.

Keywords


Carry-Propagation Free Adder, Co-Processor, FPGA, VHDL, RR-4, Xilinx ISE.

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References


M. De and B. P. Sinha, “Fast Parallel multiplication using redundant quarternary number system”, Parallel Processing Letters, Vol. , pp. 13-23 1997.

S. Nakamura, “Algorithms for iterative array multiplication”, IEEE Trans. Comput., Vol.35, pp.713-719, 1986.

N. Takagi, H. Yassura, S Yajima, “High Speed VLSI multiplication algorithm with a redundant binary addition tree”, IEEE Trans. Compute. Vol. 34, pp. 789-796, 1985.

B. P. Sinha and P. K. Srimani, “Fast parallel algorithms for binary multiplication and their implementation on systolic architectures”, IEEE Trans. Comput., Vol. 38, pp. 424-431, 1989.

K. Hwang, “Computer Arithmetic: Principles, Architecture, and Design”. NY: Wiley, 1979.

A. Avizienis, “Signed Digit Number Representation for Fast Parallel Arithmetic”, IRE Transactions on Electronic Computers, vol. EC-10, pp. 389400, September 1961.

J. E. Robertson, “A New Class of Digital Division Methods”, IRE Transactions on Electronic Computers, vol. EC-7, pp. 218-222, September 1958.

D. E. Atkins, “Higher-Radix Division Using Estimates of the Divisor and Partial Remainders”, ZEEE Transactions on Computers, vol. C-17, no. 10, pp. 925-934, October 1968.

M. D. Ercegovac and T. Lang, “Simple Radix-4 Division with Operands Scaling”, IEEE Transactions on Computers, vol. C-39, no. 9, pp. 1204-1208, September 1990.

P. Montuschi and L. Ciminiera, “Algorithm and Architectures for Radix-4 Division with Over-redundant Digit Set and Simple Digit Selection Hardware”, in 25th Asilomar Conference on Signals, Systems and Computers, (Pacific Grove, CA), pp. 418-422, November 1991.

P. Montuschi and L. Ciminiera,” Design of a Radix- 4 Division Unit with Simple Selection Table”, IEEE Transactions on Computers, vol. 41, no. 12, pp. 1606- 1611, December 1992.

B. Parhami, “Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations”, IEEE Transactions on Computers, vol. C-39, pp. 89-98, January 1990.

Naveenkumar M and Sunil S. Mathad, “Implementation of Multiplication using Redundant Radix-4 Number System on FPGA”, National Conference on Computers, Communication & Controls -11 (N4C11), 29th and 30th April 2011.

N. Burgess, “A Fast Division Algorithm for VLSI,” in Proc. of IEEE International Conference on Computer Design: VLSI in Computers and Processors, (Boston, MA), pp. 560-563, October 1991.

Hosahalli R. Srinivas ,Keshab K. Parhi , “A Fast Radix 4 Division Algorithm”, Dept. of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455


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