A Novel Modulo (2n + 1) Multiplication Approach for IDEA Cipher
Abstract
Keywords
Full Text:
PDFReferences
.W. Chen and R.H. Yao. Efficient modulo 2n + 1 multipliers for diminished-1 representation. Circuits, Devices Systems, IET, 4(4):291 -300, jul. 2010.
L. Leibowitz. A simplified binary arithmetic for the fermat number transform, Acoustics, Speech and Signal Processing, IEEE Transactions on, 24(5):356 - 359,oct. 1976.
H. T. Vergos, D. Bakalis, and C. Efstathiou. Fast modulo 2n+1 multi-operand adders and residue generators. Integr. VLSI J., 43(1):42- 48, 2010.
X.Lai and J.L Massey “A Proposal for a New Block Encryption Standard,” in advances in Cryptology – EUROCRYPT 90,Berlia,Germany: Springer Verlag pp. 389-404, 1990.
Tsoi Kuen Hung,Leong,” Cryptographic Primitives on Reconfigurable Platforms”, PhD thesis,The Chinese University of Hong Kong,2002.
R.Zimmermann,A.Curiger,H.Bonnenberg,H.Kaeslin,N.Felher,W.Fitchner,”A 177 Mb/s VLSI Implementation of the International Data Encryption Algorithm”, IEEE Journal of Solid State Circuit,vol.29,110.3,pp.303-307,March 1994.
Thaduri,M.,Yoo,S. and Gaede,R, “ An Efficient Implementation of IDEA encryption algorithm using VHDL”, ©2004 Elsevier.
P. Kitsos *, N. Sklavos, M.D. Galanis, O. Koufopavlou , “64 Bit Block ciphers: Hardware Implementations and Comparison analysis”,593-604,3rd November,2004,Elsevier.
Stefan Wolter,Hogler Matz,Andreas Schubert and Ruiner Laur, “ On the VLSI Implementation of International Data Encryption Algorithm.”, © IEEE 1995.
Sousa L , Chaves R : ‘ A universal architecture for designing efficient modulo 2n + 1 multipliers’ , IEEE Trans. Circuits Syst. I., 2005, 52, (6), pp. 1166-1178.
Efstathiou C, Vergos H.T. ,Dimitrakopoulos G., Nikolos D, : ‘Efficient diminished-1 modulo 2n + 1 multipliers ’, IEEE Trans. Comput., 2005, 54,(4), pp. 491-496.
Curiger,Bonnenberg and Kaeslin,H., “Regular VLSI Architecture for Multiplication Modulo (2n + 1).”,IEEE Journal of Solid State Circuits,vol.27,NO. 7,July 1991,pp 990-994.
Bruce Schneier,”Applied Cryptography”, 2nd Edition,Wiley publications.
Zimmermann, R.; , "Efficient VLSI implementation of modulo (2n±1) addition and multiplication," Computer Arithmetic, 1999. Proceedings. 14th IEEE Symposium on , vol., no., pp.158-167, 1999
doi: 10.1109/ARITH.1999.762841
Efstathiou, C.; Voyiatzis, I.; , "Handling zero in diminished-1 modulo 2n + 1 subtraction," Signals, Circuits and Systems (SCS), 2009 3rd International Conference on , vol., no., pp.1-6, 6-8 Nov. 2009
doi: 10.1109/ICSCS.2009.5414182.
Helger Lipmaa. Idea: A cipher for multimedia architectures, In Selected Areas in Cryptography 98, pages 248{263. Springer-Verlag, 1998.
H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, and Xuejia Lai. Vlsi implementation of a new block cipher. In Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, ICCD ’91, pages 510–513, Washington, DC, USA, 1991. IEEE Computer Society.
O. Mencer, M. Morf, and M.J. Flynn. Hardware software tri-design ofencryption for mobile communication units. In Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on, volume 5, pages 3045 –3048 vol.5, May 1998.
Refbacks
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.